Re: (subset) [PATCH v3 0/7] Add PCIe support to Sophgo SG2042 SoC
Manivannan Sadhasivam <[email protected]>
| Newsgroups | dev.linux.lists.sophgo,org.infradead.lists.linux-riscv,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-kernel,org.kernel.vger.linux-pci |
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| Message-ID | <[email protected]> |
On Fri, 12 Sep 2025 10:35:10 +0800, Chen Wang wrote: > From: Chen Wang <[email protected]> > > Sophgo's SG2042 SoC uses Cadence PCIe core to implement RC mode. > > This is a completely rewritten PCIe driver for SG2042. It inherits > some previously submitted patch codes (not merged into the upstream > mainline), but the biggest difference is that the support for > compatibility with old 32-bit PCIe devices has been removed in this > new version. This is because after discussing with community users, > we felt that there was not much demand for support for old devices, > so we made a new design based on the simplified design and practical > needs. If someone really needs to play with old devices, we can provide > them with some necessary hack patches in the downstream repository. > > [...] Applied, thanks! [1/7] dt-bindings: pci: Add Sophgo SG2042 PCIe host commit: 4e4a4f58bed19e1a3a5a7c3a18ce3b927b76fcd3 [2/7] PCI: cadence: Check pcie-ops before using it commit: 49a6c160ad4812476f8ae1a8f4ed6d15adfa6c09 [3/7] PCI: sg2042: Add Sophgo SG2042 PCIe driver commit: 1c72774df028429836eec3394212f2921bb830fc Best regards, -- Manivannan Sadhasivam <[email protected]>