Re: [PATCH v3 4/7] riscv: sophgo: dts: add PCIe controllers for SG2042
Manivannan Sadhasivam <[email protected]>
| Newsgroups | dev.linux.lists.sophgo,org.infradead.lists.linux-riscv,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-kernel,org.kernel.vger.linux-pci |
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| Message-ID | <cwc3hnre3s3rvzcgzjdbdrhlrizz4obifwragusrixa5owj5qg@yotfd3l3qxf4> |
On Fri, Sep 12, 2025 at 10:36:50AM +0800, Chen Wang wrote: > From: Chen Wang <[email protected]> > > Add PCIe controller nodes in DTS for Sophgo SG2042. > Default they are disabled. > > Signed-off-by: Inochi Amaoto <[email protected]> > Signed-off-by: Han Gao <[email protected]> > Signed-off-by: Chen Wang <[email protected]> > --- > arch/riscv/boot/dts/sophgo/sg2042.dtsi | 88 ++++++++++++++++++++++++++ > 1 file changed, 88 insertions(+) > > diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi > index b3e4d3c18fdc..b521f674283e 100644 > --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi > +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi > @@ -220,6 +220,94 @@ clkgen: clock-controller@7030012000 { > #clock-cells = <1>; > }; > > + pcie_rc0: pcie@7060000000 { > + compatible = "sophgo,sg2042-pcie-host"; > + device_type = "pci"; > + reg = <0x70 0x60000000 0x0 0x00800000>, > + <0x40 0x00000000 0x0 0x00001000>; > + reg-names = "reg", "cfg"; > + linux,pci-domain = <0>; > + #address-cells = <3>; > + #size-cells = <2>; > + ranges = <0x01000000 0x0 0xc0000000 0x40 0xc0000000 0x0 0x00400000>, PCI address of the I/O port starts from 0. So this should be: <0x01000000 0x0 0x00000000 0x40 0xc0000000 0x0 0x00400000>, Same comment for other nodes. With this fixed, Acked-by: Manivannan Sadhasivam <[email protected]> - Mani > + <0x42000000 0x0 0xd0000000 0x40 0xd0000000 0x0 0x10000000>, > + <0x02000000 0x0 0xe0000000 0x40 0xe0000000 0x0 0x20000000>, > + <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>, > + <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>; > + bus-range = <0x0 0xff>; > + vendor-id = <0x1f1c>; > + device-id = <0x2042>; > + cdns,no-bar-match-nbits = <48>; > + msi-parent = <&msi>; > + status = "disabled"; > + }; > + > + pcie_rc1: pcie@7060800000 { > + compatible = "sophgo,sg2042-pcie-host"; > + device_type = "pci"; > + reg = <0x70 0x60800000 0x0 0x00800000>, > + <0x44 0x00000000 0x0 0x00001000>; > + reg-names = "reg", "cfg"; > + linux,pci-domain = <1>; > + #address-cells = <3>; > + #size-cells = <2>; > + ranges = <0x01000000 0x0 0xc0400000 0x44 0xc0400000 0x0 0x00400000>, > + <0x42000000 0x0 0xd0000000 0x44 0xd0000000 0x0 0x10000000>, > + <0x02000000 0x0 0xe0000000 0x44 0xe0000000 0x0 0x20000000>, > + <0x43000000 0x46 0x00000000 0x46 0x00000000 0x2 0x00000000>, > + <0x03000000 0x45 0x00000000 0x45 0x00000000 0x1 0x00000000>; > + bus-range = <0x0 0xff>; > + vendor-id = <0x1f1c>; > + device-id = <0x2042>; > + cdns,no-bar-match-nbits = <48>; > + msi-parent = <&msi>; > + status = "disabled"; > + }; > + > + pcie_rc2: pcie@7062000000 { > + compatible = "sophgo,sg2042-pcie-host"; > + device_type = "pci"; > + reg = <0x70 0x62000000 0x0 0x00800000>, > + <0x48 0x00000000 0x0 0x00001000>; > + reg-names = "reg", "cfg"; > + linux,pci-domain = <2>; > + #address-cells = <3>; > + #size-cells = <2>; > + ranges = <0x01000000 0x0 0xc0800000 0x48 0xc0800000 0x0 0x00400000>, > + <0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>, > + <0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>, > + <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>, > + <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>; > + bus-range = <0x0 0xff>; > + vendor-id = <0x1f1c>; > + device-id = <0x2042>; > + cdns,no-bar-match-nbits = <48>; > + msi-parent = <&msi>; > + status = "disabled"; > + }; > + > + pcie_rc3: pcie@7062800000 { > + compatible = "sophgo,sg2042-pcie-host"; > + device_type = "pci"; > + reg = <0x70 0x62800000 0x0 0x00800000>, > + <0x4c 0x00000000 0x0 0x00001000>; > + reg-names = "reg", "cfg"; > + linux,pci-domain = <3>; > + #address-cells = <3>; > + #size-cells = <2>; > + ranges = <0x01000000 0x0 0xc0c00000 0x4c 0xc0c00000 0x0 0x00400000>, > + <0x42000000 0x0 0xf8000000 0x4c 0xf8000000 0x0 0x04000000>, > + <0x02000000 0x0 0xfc000000 0x4c 0xfc000000 0x0 0x04000000>, > + <0x43000000 0x4e 0x00000000 0x4e 0x00000000 0x2 0x00000000>, > + <0x03000000 0x4d 0x00000000 0x4d 0x00000000 0x1 0x00000000>; > + bus-range = <0x0 0xff>; > + vendor-id = <0x1f1c>; > + device-id = <0x2042>; > + cdns,no-bar-match-nbits = <48>; > + msi-parent = <&msi>; > + status = "disabled"; > + }; > + > clint_mswi: interrupt-controller@7094000000 { > compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi"; > reg = <0x00000070 0x94000000 0x00000000 0x00004000>; > -- > 2.34.1 > -- மணிவண்ணன் சதாசிவம்