[PATCH v2 1/2] tools/x86/kcpuid: Update bitfields to x86-cpuid-db v3.1
Maciej Wieczor-Retman <[email protected]> Wed, 03 Jun 2026 17:10:49 +0000
| Newsgroups | dev.linux.lists.x86-cpuid,org.kernel.vger.linux-kernel |
|---|---|
| Message-ID | <cbe9ff395b3269e112ff7ca414d726ffd7bf0787.1780506200.git.m.wieczorretman@pm.me> |
From: Maciej Wieczor-Retman <[email protected]> Update kcpuid's CSV file to version 3.1, as generated by x86-cpuid-db. Summary of the v3.1 changes: * Fix a few typos that were found during the kernel CPUID data model review. Also include fixes found using an LLM agent review. * Rename thrd_director_nclasses to hw_feedback_nclasses as it's the name used in Intel SDM. Link: https://gitlab.com/x86-cpuid.org/x86-cpuid-db/-/blob/v3.1/CHANGELOG.r= st Signed-off-by: Maciej Wieczor-Retman <[email protected]> --- tools/arch/x86/kcpuid/cpuid.csv | 52 ++++++++++++++++----------------- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/tools/arch/x86/kcpuid/cpuid.csv b/tools/arch/x86/kcpuid/cpuid.= csv index 9f5155c825ca..45a876d3519f 100644 --- a/tools/arch/x86/kcpuid/cpuid.csv +++ b/tools/arch/x86/kcpuid/cpuid.csv @@ -1,5 +1,5 @@ # SPDX-License-Identifier: CC0-1.0 -# Generator: x86-cpuid-db v3.0 +# Generator: x86-cpuid-db v3.1 =20 # # Auto-generated file. @@ -177,7 +177,7 @@ 0x6, 0, ebx, 3:0, n_therm_thresholds , Digital = thermometer thresholds 0x6, 0, ecx, 0, aperfmperf , MPERF/AP= ERF MSRs (effective frequency interface) 0x6, 0, ecx, 3, epb , IA32_ENE= RGY_PERF_BIAS MSR - 0x6, 0, ecx, 15:8, thrd_director_nclasses , Number o= f classes, Intel thread director + 0x6, 0, ecx, 15:8, hw_feedback_nclasses , Number o= f Intel Thread Director classes 0x6, 0, edx, 0, perfcap_reporting , Performa= nce capability reporting 0x6, 0, edx, 1, encap_reporting , Energy e= fficiency capability reporting 0x6, 0, edx, 11:8, feedback_sz , Feedback= interface structure size, in 4K pages @@ -247,10 +247,10 @@ 0x7, 0, edx, 1, sgx_keys , Intel SG= X attestation services 0x7, 0, edx, 2, avx512_4vnniw , AVX-512 = neural network instructions 0x7, 0, edx, 3, avx512_4fmaps , AVX-512 = multiply accumulation single precision - 0x7, 0, edx, 4, fsrm , Fast sho= rt REP MOV + 0x7, 0, edx, 4, fsrm , Fast sho= rt REP MOVSB 0x7, 0, edx, 5, uintr , User int= errupts 0x7, 0, edx, 8, avx512_vp2intersect , VP2INTER= SECT{D,Q} instructions - 0x7, 0, edx, 9, srdbs_ctrl , SRBDS mi= tigation MSR + 0x7, 0, edx, 9, srbds_ctrl , SRBDS mi= tigation MSR 0x7, 0, edx, 10, md_clear , VERW MD_= CLEAR microcode 0x7, 0, edx, 11, rtm_always_abort , XBEGIN (= RTM transaction) always aborts 0x7, 0, edx, 13, tsx_force_abort , MSR TSX_= FORCE_ABORT, RTM_ABORT bit @@ -296,8 +296,8 @@ 0x7, 2, edx, 0, intel_psfd , Intel pr= edictive store forward disable 0x7, 2, edx, 1, ipred_ctrl , MSR bits= IA32_SPEC_CTRL.IPRED_DIS_{U,S} 0x7, 2, edx, 2, rrsba_ctrl , MSR bits= IA32_SPEC_CTRL.RRSBA_DIS_{U,S} - 0x7, 2, edx, 3, ddp_ctrl , MSR bit = IA32_SPEC_CTRL.DDPD_U - 0x7, 2, edx, 4, bhi_ctrl , MSR bit = IA32_SPEC_CTRL.BHI_DIS_S + 0x7, 2, edx, 3, ddp_ctrl , MSR bit = IA32_SPEC_CTRL.DDPD_U + 0x7, 2, edx, 4, bhi_ctrl , MSR bit = IA32_SPEC_CTRL.BHI_DIS_S 0x7, 2, edx, 5, mcdt_no , MCDT mit= igation not needed 0x7, 2, edx, 6, uclock_disable , UC-lock = disable =20 @@ -368,7 +368,7 @@ 0xd, 1, ecx, 8, xss_pt , PT state 0xd, 1, ecx, 10, xss_pasid , PASID st= ate 0xd, 1, ecx, 11, xss_cet_u , CET user= state - 0xd, 1, ecx, 12, xss_cet_p , CET supe= rvisor state + 0xd, 1, ecx, 12, xss_cet_s , CET supe= rvisor state 0xd, 1, ecx, 13, xss_hdc , HDC stat= e 0xd, 1, ecx, 14, xss_uintr , UINTR st= ate 0xd, 1, ecx, 15, xss_lbr , LBR stat= e @@ -433,7 +433,7 @@ 0x12, 1, eax, 7, secs_attr_kss , Key Sepa= ration and Sharing 0x12, 1, eax, 10, secs_attr_aexnotify , Enclave = threads: AEX notifications 0x12, 1, ecx, 0, xfrm_x87 , Enclave = XFRM.X87 - 0x12, 1, ecx, 1, xfrm_sse , Enclave = XFRM.SEE + 0x12, 1, ecx, 1, xfrm_sse , Enclave = XFRM.SSE 0x12, 1, ecx, 2, xfrm_avx , Enclave = XFRM.AVX 0x12, 1, ecx, 3, xfrm_mpx_bndregs , Enclave = XFRM.BNDREGS (MPX BND0-BND3 registers) 0x12, 1, ecx, 4, xfrm_mpx_bndcsr , Enclave = XFRM.BNDCSR (MPX BNDCFGU/BNDSTATUS registers) @@ -466,9 +466,9 @@ 0x14, 0, ecx, 0, topa_output , ToPA out= put scheme 0x14, 0, ecx, 1, topa_multiple_entries , ToPA tab= les can hold multiple entries 0x14, 0, ecx, 2, single_range_output , Single-r= ange output - 0x14, 0, ecx, 3, trance_transport_output, Trace Tr= ansport subsystem output + 0x14, 0, ecx, 3, trace_transport_output , Trace Tr= ansport subsystem output 0x14, 0, ecx, 31, ip_payloads_lip , IP paylo= ads have LIP values (CS base included) - 0x14, 1, eax, 2:0, num_address_ranges , Number o= f configurable Address Ranges + 0x14, 1, eax, 2:0, num_address_ranges , Number o= f configurable address ranges 0x14, 1, eax, 31:16, mtc_periods_bmp , MTC peri= od encodings bitmap 0x14, 1, ebx, 15:0, cycle_thresholds_bmp , Cycle Th= reshold encodings bitmap 0x14, 1, ebx, 31:16, psb_periods_bmp , Configur= able PSB frequency encodings bitmap @@ -494,7 +494,7 @@ 0x17, 0, ebx, 15:0, soc_vendor_id , SoC vend= or ID 0x17, 0, ebx, 16, is_vendor_scheme , Assigned= by industry enumeration scheme (not Intel) 0x17, 0, ecx, 31:0, soc_proj_id , SoC proj= ect ID, assigned by vendor - 0x17, 0, edx, 31:0, soc_stepping_id , Soc proj= ect stepping ID, assigned by vendor + 0x17, 0, edx, 31:0, soc_stepping_id , SoC proj= ect stepping ID, assigned by vendor 0x17, 3:1, eax, 31:0, vendor_brand_a , Vendor B= rand ID string, bytes subleaf_nr * (0 -> 3) 0x17, 3:1, ebx, 31:0, vendor_brand_b , Vendor B= rand ID string, bytes subleaf_nr * (4 -> 7) 0x17, 3:1, ecx, 31:0, vendor_brand_c , Vendor B= rand ID string, bytes subleaf_nr * (8 -> 11) @@ -514,12 +514,12 @@ 0x18, 31:0, edx, 4:0, tlb_type , Translat= ion cache type (TLB type) 0x18, 31:0, edx, 7:5, tlb_cache_level , Translat= ion cache level (1-based) 0x18, 31:0, edx, 8, is_fully_associative , Fully-as= sociative - 0x18, 31:0, edx, 25:14, tlb_max_addressible_ids, Max numb= er of addressable IDs - 1 + 0x18, 31:0, edx, 25:14, tlb_max_addressable_ids, Max numb= er of addressable IDs - 1 =20 # Leaf 19H # Intel key locker =20 - 0x19, 0, eax, 0, kl_cpl0_only , CPL0-onl= y key Locker restriction + 0x19, 0, eax, 0, kl_cpl0_only , CPL0-onl= y key locker restriction 0x19, 0, eax, 1, kl_no_encrypt , No-encry= pt key locker restriction 0x19, 0, eax, 2, kl_no_decrypt , No-decry= pt key locker restriction 0x19, 0, ebx, 0, aes_keylocker , AES key = locker instructions @@ -546,7 +546,7 @@ # Intel LBR (Last Branch Record) =20 0x1c, 0, eax, 7:0, lbr_depth_mask , Max LBR = stack depth bitmask - 0x1c, 0, eax, 30, lbr_deep_c_reset , LBRs may= be cleared on MWAIT C-state > C1 + 0x1c, 0, eax, 30, lbr_deep_c_reset , LBRs may= be cleared on MWAIT C-state > C1 0x1c, 0, eax, 31, lbr_ip_is_lip , LBR IP c= ontain Last IP (otherwise effective IP) 0x1c, 0, ebx, 0, lbr_cpl , CPL filt= ering 0x1c, 0, ebx, 1, lbr_branch_filter , Branch f= iltering @@ -591,8 +591,8 @@ # Intel TD (Trust Domain) =20 0x21, 0, ebx, 31:0, tdx_vendorid_0 , TDX vend= or ID string bytes 0 - 3 - 0x21, 0, ecx, 31:0, tdx_vendorid_2 , CPU vend= or ID string bytes 8 - 11 - 0x21, 0, edx, 31:0, tdx_vendorid_1 , CPU vend= or ID string bytes 4 - 7 + 0x21, 0, ecx, 31:0, tdx_vendorid_2 , TDX vend= or ID string bytes 8 - 11 + 0x21, 0, edx, 31:0, tdx_vendorid_1 , TDX vend= or ID string bytes 4 - 7 =20 # Leaf 23H # Intel Architectural Performance Monitoring Extended (ArchPerfmonExt) @@ -857,7 +857,7 @@ 0x8000000a, 0, edx, 1, lbrv , LBR virt= ualization 0x8000000a, 0, edx, 2, svm_lock , SVM lock 0x8000000a, 0, edx, 3, nrip_save , NRIP sav= e support on #VMEXIT -0x8000000a, 0, edx, 4, tsc_scale , MSR base= d TSC rate control +0x8000000a, 0, edx, 4, tsc_scale , MSR-base= d TSC rate control 0x8000000a, 0, edx, 5, vmcb_clean , VMCB cle= an bits support 0x8000000a, 0, edx, 6, flushbyasid , Flush by= ASID + Extended VMCB TLB_Control 0x8000000a, 0, edx, 7, decodeassists , Decode A= ssists support @@ -895,7 +895,7 @@ =20 0x8000001a, 0, eax, 0, fp_128 , Internal= FP/SIMD exec data path is 128-bits wide 0x8000001a, 0, eax, 1, movu_preferred , SSE: MOV= U* better than MOVL*/MOVH* -0x8000001a, 0, eax, 2, fp_256 , internal= FP/SSE exec data path is 256-bits wide +0x8000001a, 0, eax, 2, fp_256 , Internal= FP/SSE exec data path is 256-bits wide =20 # Leaf 8000001BH # AMD IBS (Instruction-Based Sampling) @@ -917,7 +917,7 @@ # AMD LWP (Lightweight Profiling) =20 0x8000001c, 0, eax, 0, os_lwp_avail , OS: LWP = is available to application programs -0x8000001c, 0, eax, 1, os_lpwval , OS: LWPV= AL instruction +0x8000001c, 0, eax, 1, os_lwpval , OS: LWPV= AL instruction 0x8000001c, 0, eax, 2, os_lwp_ire , OS: Inst= ructions Retired Event 0x8000001c, 0, eax, 3, os_lwp_bre , OS: Bran= ch Retired Event 0x8000001c, 0, eax, 4, os_lwp_dme , OS: Dcac= he Miss Event @@ -934,13 +934,13 @@ 0x8000001c, 0, ecx, 5, lwp_data_addr , Cache mi= ss events report data cache address 0x8000001c, 0, ecx, 8:6, lwp_latency_rnd , Cache la= tency rounding amount 0x8000001c, 0, ecx, 15:9, lwp_version , LWP vers= ion -0x8000001c, 0, ecx, 23:16, lwp_buf_min_sz , LWP even= t ring buffer min size, 32 event records units +0x8000001c, 0, ecx, 23:16, lwp_buf_min_sz , LWP even= t ring buffer min size, 32 event record units 0x8000001c, 0, ecx, 28, lwp_branch_predict , Branches= Retired events can be filtered 0x8000001c, 0, ecx, 29, lwp_ip_filtering , IP filte= ring (IPI, IPF, BaseIP, and LimitIP @ LWPCP) 0x8000001c, 0, ecx, 30, lwp_cache_levels , Cache-re= lated events: filter by cache level 0x8000001c, 0, ecx, 31, lwp_cache_latency , Cache-re= lated events: filter by latency 0x8000001c, 0, edx, 0, hw_lwp_avail , HW: LWP = available -0x8000001c, 0, edx, 1, hw_lpwval , HW: LWPV= AL available +0x8000001c, 0, edx, 1, hw_lwpval , HW: LWPV= AL available 0x8000001c, 0, edx, 2, hw_lwp_ire , HW: Inst= ructions Retired Event 0x8000001c, 0, edx, 3, hw_lwp_bre , HW: Bran= ch Retired Event 0x8000001c, 0, edx, 4, hw_lwp_dme , HW: Dcac= he Miss Event @@ -1040,8 +1040,8 @@ 0x80000021, 0, eax, 7, upper_addr_ignore , EFER MSR= Upper Address Ignore 0x80000021, 0, eax, 8, autoibrs , EFER MSR= Automatic IBRS 0x80000021, 0, eax, 9, no_smm_ctl_msr , SMM_CTL = MSR not available -0x80000021, 0, eax, 10, fsrs , Fast Sho= rt Rep STOSB -0x80000021, 0, eax, 11, fsrc , Fast Sho= rt Rep CMPSB +0x80000021, 0, eax, 10, fsrs , Fast Sho= rt REP STOSB +0x80000021, 0, eax, 11, fsrc , Fast Sho= rt REP CMPSB 0x80000021, 0, eax, 13, prefetch_ctl_msr , Prefetch= control MSR 0x80000021, 0, eax, 16, opcode_reclaim , Reserves= opcode space 0x80000021, 0, eax, 17, user_cpuid_disable , #GP when= executing CPUID at CPL > 0 @@ -1093,9 +1093,9 @@ # Maximum Transmeta leaf + CPU vendor string =20 0x80860000, 0, eax, 31:0, max_tra_leaf , Maximum = Transmeta leaf -0x80860000, 0, ebx, 31:0, cpu_vendorid_0 , Transmet= a Vendor ID string bytes 0 - 3 -0x80860000, 0, ecx, 31:0, cpu_vendorid_2 , Transmet= a Vendor ID string bytes 8 - 11 -0x80860000, 0, edx, 31:0, cpu_vendorid_1 , Transmet= a Vendor ID string bytes 4 - 7 +0x80860000, 0, ebx, 31:0, cpu_vendorid_0 , Transmet= a vendor ID string bytes 0 - 3 +0x80860000, 0, ecx, 31:0, cpu_vendorid_2 , Transmet= a vendor ID string bytes 8 - 11 +0x80860000, 0, edx, 31:0, cpu_vendorid_1 , Transmet= a vendor ID string bytes 4 - 7 =20 # Leaf 80860001H # Transmeta extended CPU features --=20 2.54.0