[PATCH v2 2/2] x86/cpuid: Update bitfields to x86-cpuid-db v3.1

From: Maciej Wieczor-Retman <[email protected]>

Update leaf_types.h to version 3.1, as generated by x86-cpuid-db.

Summary of the v3.1 changes:

* Fix a few typos that were found during the kernel CPUID data model
  review. Also include fixes found using an LLM agent review.

* Rename thrd_director_nclasses to hw_feedback_nclasses as it's the
  name used in Intel SDM.

Link: https://gitlab.com/x86-cpuid.org/x86-cpuid-db/-/blob/v3.1/CHANGELOG.r=
st
Signed-off-by: Maciej Wieczor-Retman <[email protected]>
---
 arch/x86/include/asm/cpuid/leaf_types.h | 62 ++++++++++++-------------
 1 file changed, 31 insertions(+), 31 deletions(-)

diff --git a/arch/x86/include/asm/cpuid/leaf_types.h b/arch/x86/include/asm=
/cpuid/leaf_types.h
index 5b0008e455e2..222d2d2682c8 100644
--- a/arch/x86/include/asm/cpuid/leaf_types.h
+++ b/arch/x86/include/asm/cpuid/leaf_types.h
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: MIT */
-/* Generator: x86-cpuid-db v3.0 */
+/* Generator: x86-cpuid-db v3.1 */
=20
 /*
  * Auto-generated file.
@@ -246,7 +246,7 @@ struct leaf_0x6_0 {
 =09=09=09=09=09=09:  2, // Reserved
 =09=09energy_perf_bias=09=09:  1, // IA32_ENERGY_PERF_BIAS MSR
 =09=09=09=09=09=09:  4, // Reserved
-=09=09thrd_director_nclasses=09=09:  8, // Number of classes, Intel thread=
 director
+=09=09hw_feedback_nclasses=09=09:  8, // Number of Intel Thread Director c=
lasses
 =09=09=09=09=09=09: 16; // Reserved
 =09// edx
 =09u32=09perfcap_reporting=09=09:  1, // Performance capability reporting
@@ -332,11 +332,11 @@ struct leaf_0x7_0 {
 =09=09sgx_keys=09=09=09:  1, // Intel SGX attestation services
 =09=09avx512_4vnniw=09=09=09:  1, // AVX-512 neural network instructions
 =09=09avx512_4fmaps=09=09=09:  1, // AVX-512 multiply accumulation single =
precision
-=09=09fsrm=09=09=09=09:  1, // Fast short REP MOV
+=09=09fsrm=09=09=09=09:  1, // Fast short REP MOVSB
 =09=09uintr=09=09=09=09:  1, // User interrupts
 =09=09=09=09=09=09:  2, // Reserved
 =09=09avx512_vp2intersect=09=09:  1, // VP2INTERSECT{D,Q} instructions
-=09=09srdbs_ctrl=09=09=09:  1, // SRBDS mitigation MSR
+=09=09srbds_ctrl=09=09=09:  1, // SRBDS mitigation MSR
 =09=09md_clear=09=09=09:  1, // VERW MD_CLEAR microcode
 =09=09rtm_always_abort=09=09:  1, // XBEGIN (RTM transaction) always abort=
s
 =09=09=09=09=09=09:  1, // Reserved
@@ -379,7 +379,7 @@ struct leaf_0x7_1 {
 =09=09wrmsrns=09=09=09=09:  1, // WRMSRNS instruction (WRMSR-non-serializi=
ng)
 =09=09nmi_src=09=09=09=09:  1, // NMI-source reporting with FRED event dat=
a
 =09=09amx_fp16=09=09=09:  1, // AMX-FP16: FP16 tile operations
-=09=09hreset =09=09=09=09:  1, // HRESET (Thread director history reset)
+=09=09hreset=09=09=09=09:  1, // HRESET (Thread director history reset)
 =09=09avx_ifma=09=09=09:  1, // Integer fused multiply add
 =09=09=09=09=09=09:  2, // Reserved
 =09=09lam=09=09=09=09:  1, // Linear address masking
@@ -414,8 +414,8 @@ struct leaf_0x7_2 {
 =09u32=09intel_psfd=09=09=09:  1, // Intel predictive store forward disabl=
e
 =09=09ipred_ctrl=09=09=09:  1, // MSR bits IA32_SPEC_CTRL.IPRED_DIS_{U,S}
 =09=09rrsba_ctrl=09=09=09:  1, // MSR bits IA32_SPEC_CTRL.RRSBA_DIS_{U,S}
-=09=09ddp_ctrl=09=09=09:  1, // MSR bit  IA32_SPEC_CTRL.DDPD_U
-=09=09bhi_ctrl=09=09=09:  1, // MSR bit  IA32_SPEC_CTRL.BHI_DIS_S
+=09=09ddp_ctrl=09=09=09:  1, // MSR bit IA32_SPEC_CTRL.DDPD_U
+=09=09bhi_ctrl=09=09=09:  1, // MSR bit IA32_SPEC_CTRL.BHI_DIS_S
 =09=09mcdt_no=09=09=09=09:  1, // MCDT mitigation not needed
 =09=09uclock_disable=09=09=09:  1, // UC-lock disable
 =09=09=09=09=09=09: 25; // Reserved
@@ -547,7 +547,7 @@ struct leaf_0xd_1 {
 =09=09=09=09=09=09:  1, // Reserved
 =09=09xss_pasid=09=09=09:  1, // PASID state
 =09=09xss_cet_u=09=09=09:  1, // CET user state
-=09=09xss_cet_p=09=09=09:  1, // CET supervisor state
+=09=09xss_cet_s=09=09=09:  1, // CET supervisor state
 =09=09xss_hdc=09=09=09=09:  1, // HDC state
 =09=09xss_uintr=09=09=09:  1, // UINTR state
 =09=09xss_lbr=09=09=09=09:  1, // LBR state
@@ -711,7 +711,7 @@ struct leaf_0x12_1 {
 =09u32=09=09=09=09=09: 32; // Reserved
 =09// ecx
 =09u32=09xfrm_x87=09=09=09:  1, // Enclave XFRM.X87
-=09=09xfrm_sse=09=09=09:  1, // Enclave XFRM.SEE
+=09=09xfrm_sse=09=09=09:  1, // Enclave XFRM.SSE
 =09=09xfrm_avx=09=09=09:  1, // Enclave XFRM.AVX
 =09=09xfrm_mpx_bndregs=09=09:  1, // Enclave XFRM.BNDREGS (MPX BND0-BND3 r=
egisters)
 =09=09xfrm_mpx_bndcsr=09=09=09:  1, // Enclave XFRM.BNDCSR (MPX BNDCFGU/BN=
DSTATUS registers)
@@ -771,7 +771,7 @@ struct leaf_0x14_0 {
 =09u32=09topa_output=09=09=09:  1, // ToPA output scheme
 =09=09topa_multiple_entries=09=09:  1, // ToPA tables can hold multiple en=
tries
 =09=09single_range_output=09=09:  1, // Single-range output
-=09=09trance_transport_output=09=09:  1, // Trace Transport subsystem outp=
ut
+=09=09trace_transport_output=09=09:  1, // Trace Transport subsystem outpu=
t
 =09=09=09=09=09=09: 27, // Reserved
 =09=09ip_payloads_lip=09=09=09:  1; // IP payloads have LIP values (CS bas=
e included)
 =09// edx
@@ -780,7 +780,7 @@ struct leaf_0x14_0 {
=20
 struct leaf_0x14_1 {
 =09// eax
-=09u32=09num_address_ranges=09=09:  3, // Number of configurable Address R=
anges
+=09u32=09num_address_ranges=09=09:  3, // Number of configurable address r=
anges
 =09=09=09=09=09=09: 13, // Reserved
 =09=09mtc_periods_bmp=09=09=09: 16; // MTC period encodings bitmap
 =09// ebx
@@ -842,7 +842,7 @@ struct leaf_0x17_0 {
 =09// ecx
 =09u32=09soc_proj_id=09=09=09: 32; // SoC project ID, assigned by vendor
 =09// edx
-=09u32=09soc_stepping_id=09=09=09: 32; // Soc project stepping ID, assigne=
d by vendor
+=09u32=09soc_stepping_id=09=09=09: 32; // SoC project stepping ID, assigne=
d by vendor
 };
=20
 struct leaf_0x17_n {
@@ -883,7 +883,7 @@ struct leaf_0x18_n {
 =09=09tlb_cache_level=09=09=09:  3, // Translation cache level (1-based)
 =09=09is_fully_associative=09=09:  1, // Fully-associative
 =09=09=09=09=09=09:  5, // Reserved
-=09=09tlb_max_addressible_ids=09=09: 12, // Max number of addressable IDs =
- 1
+=09=09tlb_max_addressable_ids=09=09: 12, // Max number of addressable IDs =
- 1
 =09=09=09=09=09=09:  6; // Reserved
 };
=20
@@ -897,7 +897,7 @@ struct leaf_0x18_n {
=20
 struct leaf_0x19_0 {
 =09// eax
-=09u32=09kl_cpl0_only=09=09=09:  1, // CPL0-only key Locker restriction
+=09u32=09kl_cpl0_only=09=09=09:  1, // CPL0-only key locker restriction
 =09=09kl_no_encrypt=09=09=09:  1, // No-encrypt key locker restriction
 =09=09kl_no_decrypt=09=09=09:  1, // No-decrypt key locker restriction
 =09=09=09=09=09=09: 29; // Reserved
@@ -962,7 +962,7 @@ struct leaf_0x1c_0 {
 =09// eax
 =09u32=09lbr_depth_mask=09=09=09:  8, // Max LBR stack depth bitmask
 =09=09=09=09=09=09: 22, // Reserved
-=09=09lbr_deep_c_reset=09=09:  1, // LBRs maybe cleared on MWAIT C-state >=
 C1
+=09=09lbr_deep_c_reset=09=09:  1, // LBRs may be cleared on MWAIT C-state =
> C1
 =09=09lbr_ip_is_lip=09=09=09:  1; // LBR IP contain Last IP (otherwise eff=
ective IP)
 =09// ebx
 =09u32=09lbr_cpl=09=09=09=09:  1, // CPL filtering
@@ -1079,9 +1079,9 @@ struct leaf_0x21_0 {
 =09// ebx
 =09u32=09tdx_vendorid_0=09=09=09: 32; // TDX vendor ID string bytes 0 - 3
 =09// ecx
-=09u32=09tdx_vendorid_2=09=09=09: 32; // CPU vendor ID string bytes 8 - 11
+=09u32=09tdx_vendorid_2=09=09=09: 32; // TDX vendor ID string bytes 8 - 11
 =09// edx
-=09u32=09tdx_vendorid_1=09=09=09: 32; // CPU vendor ID string bytes 4 - 7
+=09u32=09tdx_vendorid_1=09=09=09: 32; // TDX vendor ID string bytes 4 - 7
 };
=20
 /*
@@ -1281,12 +1281,12 @@ struct leaf_0x4c780001_0 {
 =09=09flexpriority=09=09=09:  1, // Intel FlexPriority
 =09=09ept=09=09=09=09:  1, // Intel Extended Page Table
 =09=09vpid=09=09=09=09:  1, // Intel Virtual Processor ID
-=09=09coherency_sfw_no=09=09:  1, // SNP cache coherency software work aro=
und not needed
+=09=09coherency_sfw_no=09=09:  1, // SNP cache coherency software workarou=
nd not needed
 =09=09=09=09=09=09: 10, // Reserved
 =09=09vmmcall=09=09=09=09:  1, // Prefer VMMCALL to VMCALL
 =09=09xenpv=09=09=09=09:  1, // Xen paravirtual guest
 =09=09ept_ad=09=09=09=09:  1, // Intel Extended Page Table access-dirty bi=
t
-=09=09VMCALL=09=09=09=09:  1, // Hypervisor supports the VMCALL instructio=
n
+=09=09vmcall=09=09=09=09:  1, // Hypervisor supports the VMCALL instructio=
n
 =09=09vmw_vmmcall=09=09=09:  1, // VMware prefers the VMMCALL instruction
 =09=09pvunlock=09=09=09:  1, // PV unlock function
 =09=09vcpupreempt=09=09=09:  1, // PV vcpu_is_preempted function
@@ -1380,11 +1380,11 @@ struct leaf_0x4c780002_0 {
 =09=09amd_e400=09=09=09:  1, // CPU is among the affected by Erratum 400
 =09=09cpu_meltdown=09=09=09:  1, // CPU affected by meltdown; needs kernel=
 page table isolation
 =09=09spectre_v1=09=09=09:  1, // CPU affected by Spectre variant 1 with c=
onditional branches
-=09=09specture_v2=09=09=09:  1, // CPU affected by Spectre variant 2 with =
indirect branches
+=09=09spectre_v2=09=09=09:  1, // CPU affected by Spectre variant 2 with i=
ndirect branches
 =09=09spec_store_bypass=09=09:  1, // CPU affected by speculative store by=
pass attack
 =09=09l1tf=09=09=09=09:  1, // CPU affected by L1 Terminal Fault
 =09=09mds=09=09=09=09:  1, // CPU affected by Microarchitectural data samp=
ling
-=09=09msbds_only=09=09=09:  1, // Microarchitectural data sampling: CPU on=
ly affected by the MSDBS variant
+=09=09msbds_only=09=09=09:  1, // Microarchitectural data sampling: CPU on=
ly affected by the MSBDS variant
 =09=09swapgs=09=09=09=09:  1, // CPU affected by speculation through SWAPG=
S
 =09=09taa=09=09=09=09:  1, // CPU is affected by TSX Async Abort (TAA)
 =09=09itlb_multihit=09=09=09:  1, // CPU may incur MCE during certain page=
 attribute changes
@@ -1732,7 +1732,7 @@ struct leaf_0x8000000a_0 {
 =09=09lbr_virt=09=09=09:  1, // LBR virtualization
 =09=09svm_lock=09=09=09:  1, // SVM lock
 =09=09nrip_save=09=09=09:  1, // NRIP save support on #VMEXIT
-=09=09tsc_rate_msr=09=09=09:  1, // MSR based TSC rate control
+=09=09tsc_rate_msr=09=09=09:  1, // MSR-based TSC rate control
 =09=09vmcb_clean=09=09=09:  1, // VMCB clean bits support
 =09=09flush_by_asid=09=09=09:  1, // Flush by ASID + Extended VMCB TLB_Con=
trol
 =09=09decode_assists=09=09=09:  1, // Decode Assists support
@@ -1790,7 +1790,7 @@ struct leaf_0x8000001a_0 {
 =09// eax
 =09u32=09fp_128=09=09=09=09:  1, // Internal FP/SIMD exec data path is 128=
-bits wide
 =09=09movu_preferred=09=09=09:  1, // SSE: MOVU* better than MOVL*/MOVH*
-=09=09fp_256=09=09=09=09:  1, // internal FP/SSE exec data path is 256-bit=
s wide
+=09=09fp_256=09=09=09=09:  1, // Internal FP/SSE exec data path is 256-bit=
s wide
 =09=09=09=09=09=09: 29; // Reserved
 =09// ebx
 =09u32=09=09=09=09=09: 32; // Reserved
@@ -1836,7 +1836,7 @@ struct leaf_0x8000001b_0 {
 struct leaf_0x8000001c_0 {
 =09// eax
 =09u32=09os_lwp_avail=09=09=09:  1, // OS: LWP is available to application=
 programs
-=09=09os_lpwval=09=09=09:  1, // OS: LWPVAL instruction
+=09=09os_lwpval=09=09=09:  1, // OS: LWPVAL instruction
 =09=09os_lwp_ire=09=09=09:  1, // OS: Instructions Retired Event
 =09=09os_lwp_bre=09=09=09:  1, // OS: Branch Retired Event
 =09=09os_lwp_dme=09=09=09:  1, // OS: Dcache Miss Event
@@ -1856,7 +1856,7 @@ struct leaf_0x8000001c_0 {
 =09=09lwp_data_addr=09=09=09:  1, // Cache miss events report data cache a=
ddress
 =09=09lwp_latency_rnd=09=09=09:  3, // Cache latency rounding amount
 =09=09lwp_version=09=09=09:  7, // LWP version
-=09=09lwp_buf_min_sz=09=09=09:  8, // LWP event ring buffer min size, 32 e=
vent records units
+=09=09lwp_buf_min_sz=09=09=09:  8, // LWP event ring buffer min size, 32 e=
vent record units
 =09=09=09=09=09=09:  4, // Reserved
 =09=09lwp_branch_predict=09=09:  1, // Branches Retired events can be filt=
ered
 =09=09lwp_ip_filtering=09=09:  1, // IP filtering (IPI, IPF, BaseIP, and L=
imitIP @ LWPCP)
@@ -1864,7 +1864,7 @@ struct leaf_0x8000001c_0 {
 =09=09lwp_cache_latency=09=09:  1; // Cache-related events: filter by late=
ncy
 =09// edx
 =09u32=09hw_lwp_avail=09=09=09:  1, // HW: LWP available
-=09=09hw_lpwval=09=09=09:  1, // HW: LWPVAL available
+=09=09hw_lwpval=09=09=09:  1, // HW: LWPVAL available
 =09=09hw_lwp_ire=09=09=09:  1, // HW: Instructions Retired Event
 =09=09hw_lwp_bre=09=09=09:  1, // HW: Branch Retired Event
 =09=09hw_lwp_dme=09=09=09:  1, // HW: Dcache Miss Event
@@ -2051,8 +2051,8 @@ struct leaf_0x80000021_0 {
 =09=09upper_addr_ignore=09=09:  1, // EFER MSR Upper Address Ignore
 =09=09auto_ibrs=09=09=09:  1, // EFER MSR Automatic IBRS
 =09=09no_smm_ctl_msr=09=09=09:  1, // SMM_CTL MSR not available
-=09=09fsrs=09=09=09=09:  1, // Fast Short Rep STOSB
-=09=09fsrc=09=09=09=09:  1, // Fast Short Rep CMPSB
+=09=09fsrs=09=09=09=09:  1, // Fast Short REP STOSB
+=09=09fsrc=09=09=09=09:  1, // Fast Short REP CMPSB
 =09=09=09=09=09=09:  1, // Reserved
 =09=09prefetch_ctl_msr=09=09:  1, // Prefetch control MSR
 =09=09=09=09=09=09:  2, // Reserved
@@ -2157,11 +2157,11 @@ struct leaf_0x80860000_0 {
 =09// eax
 =09u32=09max_tra_leaf=09=09=09: 32; // Maximum Transmeta leaf
 =09// ebx
-=09u32=09cpu_vendorid_0=09=09=09: 32; // Transmeta Vendor ID string bytes =
0 - 3
+=09u32=09cpu_vendorid_0=09=09=09: 32; // Transmeta vendor ID string bytes =
0 - 3
 =09// ecx
-=09u32=09cpu_vendorid_2=09=09=09: 32; // Transmeta Vendor ID string bytes =
8 - 11
+=09u32=09cpu_vendorid_2=09=09=09: 32; // Transmeta vendor ID string bytes =
8 - 11
 =09// edx
-=09u32=09cpu_vendorid_1=09=09=09: 32; // Transmeta Vendor ID string bytes =
4 - 7
+=09u32=09cpu_vendorid_1=09=09=09: 32; // Transmeta vendor ID string bytes =
4 - 7
 };
=20
 /*
--=20
2.54.0