Re: [PATCH 6.12.y-cip v2 07/10] dt-bindings: pinctrl: renesas,r9a09g077: Document pin configuration properties
Pavel Machek <[email protected]> Tue, 7 Jul 2026 22:17:45 +0200
| Newsgroups | org.cip-project.lists.cip-dev |
|---|---|
| Message-ID | <[email protected]> |
Hi!
> +++ b/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml
> @@ -72,6 +72,23 @@ definitions:
> input: true
> input-enable: true
> output-enable: true
> + bias-disable: true
> + bias-pull-down: true
> + bias-pull-up: true
> + input-schmitt-enable: true
> + input-schmitt-disable: true
> + slew-rate:
> + description: 0 is slow slew rate, 1 is fast slew rate
> + enum: [0, 1]
Elsewhere in tree we have
Documentation/devicetree/bindings/clock/renesas,9series.yaml
renesas,slew-rate:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [ 2000000, 3000000 ]
description: Output clock slew rate select in V/ns
atmel,at91-pio4-pinctrl.txt:
- for microchip,sama7g5-pinctrl only:
- slew-rate: 0 - disabled, 1 - enabled (default)
I guess having one solution would be best, and specifying real units
(V/ns) rather than fast/slow seems good to me.
Best regards,
Pavel
signature.asc
(application/pgp-signature, 195 B)
-----BEGIN PGP SIGNATURE----- iF0EABECAB0WIQRPfPO7r0eAhk010v0w5/Bqldv68gUCak1e6QAKCRAw5/Bqldv6 8iWHAJ0fyfvkGmHQbmXPhhvdi0UQQojg4wCcC4IVR+jajcwZeoBll9jB5dFV2jc= =3sIH -----END PGP SIGNATURE-----