RE: [PATCH 6.12.y-cip 00/26] Add RZ/G3L IA55 support

Hi all,

> -----Original Message-----
> From: Biju <[email protected]>
> Sent: Friday, July 3, 2026 7:07 PM
> To: [email protected]; iwamatsu nobuhiro(岩松 信洋 □ＤＩＴＣ○
> ＣＰＴ) <[email protected]>; Pavel Machek
> <[email protected]>
> Cc: Biju Das <[email protected]>; Lad Prabhakar
> <[email protected]>
> Subject: [PATCH 6.12.y-cip 00/26] Add RZ/G3L IA55 support
> 
> From: Biju Das <[email protected]>
> 
> The IRQC block on the RZ/G3L SoC is almost identical to the one found on the
> RZ/G2L SoC, with the following differences:
> 
>  - The number of GPIO interrupts for TINT selection is 113 instead of 123.
>  - The pin index and TINT selection index are not in the 1:1 map.
>  - The number of external interrupts are 16 instead of 8, out of these
>    8 external interrupts are shared with TINT.
> 
> All the patches in this series are cherry-picked from mainline.
> 
> Biju Das (19):
>   irqchip/renesas-rzg2l: Fix error path in rzg2l_irqc_common_probe()
>   irqchip/renesas-rzg2l: Drop redundant IRQC_TINT_START check in
>     rzg2l_irqc_alloc()
>   irqchip/renesas-rzg2l: Replace single irq_chip with per-region
>     irq_chip instances
>   irqchip/renesas-rzg2l: Split EOI handler into separate IRQ and TINT
>     functions
>   irqchip/renesas-rzg2l: Split set_type handler into separate IRQ and
>     TINT functions
>   irqchip/renesas-rzg2l: Replace rzg2l_irqc_irq_{enable,disable} with
>     TINT-specific handlers
>   irqchip/renesas-rzg2l: Split rzfive_tint_irq_endisable() into separate
>     IRQ and TINT helpers
>   irqchip/renesas-rzg2l: Split rzfive_irqc_{mask,unmask} into separate
>     IRQ and TINT handlers
>   irqchip/renesas-rzg2l: Dynamically allocate fwspec array
>   irqchip/renesas-rzg2l: Drop IRQC_NUM_IRQ macro
>   irqchip/renesas-rzg2l: Drop IRQC_TINT_START macro
>   irqchip/renesas-rzg2l: Drop IRQC_IRQ_COUNT macro
>   dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Use pattern for
>     interrupt-names
>   dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3L
>     SoC
>   irqchip/renesas-rzg2l: Add RZ/G3L support
>   irqchip/renesas-rzg2l: Add shared interrupt support
>   irqchip/renesas-rzg2l: Replace raw_spin_{lock,unlock} with guard() in
>     rzg2l_irq_set_type()
>   irqchip/renesas-rzg2l: Clear the shared interrupt bit in
>     rzg2l_irqc_free()
>   irqchip/renesas-rzg2l: Add NMI support
> 
> Fabrizio Castro (6):
>   irqchip/renesas-rzg2l: Use local dev pointer in
>     rzg2l_irqc_common_init()
>   irqchip/renesas-rzg2l: Use
>     devm_reset_control_get_exclusive_deasserted()
>   irqchip/renesas-rzg2l: Use devm_pm_runtime_enable()
>   irqchip/renesas-rzg2l: Remove pm_put label
>   irqchip/renesas-rzg2l: Switch to using dev_err_probe()
>   irqchip/renesas-rzg2l: Simplify checks in rzg2l_irqc_common_init()
> 
> Xichao Zhao (1):
>   irqchip/renesas-rzg2l: Remove dev_err_probe() if error is -ENOMEM
> 
>  .../renesas,rzg2l-irqc.yaml                   | 157 ++---
>  drivers/irqchip/irq-renesas-rzg2l.c           | 627
> ++++++++++++++----
>  2 files changed, 536 insertions(+), 248 deletions(-)
> 

I reviewed this series, There doesn't seem to be a issue.
I can apply if there are no other comments and no test issues.

Reviewed-by: Nobuhiro Iwamatsu <[email protected]>

Test: https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/2659938341