Re: [cip-dev] [PATCH v2 6.1.y-cip] i3c: master: dw: stop hardcoding initial speed

Hi!

> From: Jack Chen <[email protected]>
> 
> commit 510d2358c466bf6588034f0d3b2266eed2bc0a51 upstream.
> 
> Bus-speed could be default(12.5MHz) or defined by users in dts.
> Dw-i3c-master should not hard-code the initial speed to be
> I3C_BUS_TYP_I3C_SCL_RATE (12.5MHz)
> And because of Synopsys's I3C controller limit (hcnt/lcnt register
> length) and core-clk provided, there is a limit to bus speed, too.
> For example, when core-clk is 250 MHz, the bus speed cannot be
> lowered below 1MHz.
> 
> Tested: tested with an i3c sensor and captured with a logic
> analyzer.

This is already in 6.12.0, so no need to do anything there. Looks good
to me.

Reviewed-by: Pavel Machek <[email protected]>

I'll apply it if it passes testing (and there are no other comments).

Best regards,
                                                                Pavel


> +++ b/drivers/i3c/master/dw-i3c-master.c
> @@ -531,7 +531,7 @@ static int dw_i3c_clk_cfg(struct dw_i3c_master *master)
>  	if (hcnt < SCL_I3C_TIMING_CNT_MIN)
>  		hcnt = SCL_I3C_TIMING_CNT_MIN;
>  
> -	lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_TYP_I3C_SCL_RATE) - hcnt;
> +	lcnt = DIV_ROUND_UP(core_rate, master->base.bus.scl_rate.i3c) - hcnt;
>  	if (lcnt < SCL_I3C_TIMING_CNT_MIN)
>  		lcnt = SCL_I3C_TIMING_CNT_MIN;
>  
> @@ -541,7 +541,8 @@ static int dw_i3c_clk_cfg(struct dw_i3c_master *master)
>  	if (!(readl(master->regs + DEVICE_CTRL) & DEV_CTRL_I2C_SLAVE_PRESENT))
>  		writel(BUS_I3C_MST_FREE(lcnt), master->regs + BUS_FREE_TIMING);
>  
> -	lcnt = DIV_ROUND_UP(I3C_BUS_TLOW_OD_MIN_NS, core_period);
> +	lcnt = max_t(u8,
> +		     DIV_ROUND_UP(I3C_BUS_TLOW_OD_MIN_NS, core_period), lcnt);
>  	scl_timing = SCL_I3C_TIMING_HCNT(hcnt) | SCL_I3C_TIMING_LCNT(lcnt);
>  	writel(scl_timing, master->regs + SCL_I3C_OD_TIMING);
>

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