RE: [cip-dev] [PATCH v2 6.1.y-cip] i3c: master: dw: stop hardcoding initial speed

Hi Pavel,

> -----Original Message-----
> From: Pavel Machek <[email protected]>
> Sent: Tuesday, July 21, 2026 7:29 PM
> To: iwamatsu nobuhiro(岩松 信洋 □ＤＩＴＣ○ＣＰＴ)
> <[email protected]>
> Cc: [email protected]; [email protected];
> [email protected]
> Subject: Re: [cip-dev] [PATCH v2 6.1.y-cip] i3c: master: dw: stop hardcoding
> initial speed
> 
> Hi!
> 
> > From: Jack Chen <[email protected]>
> >
> > commit 510d2358c466bf6588034f0d3b2266eed2bc0a51 upstream.
> >
> > Bus-speed could be default(12.5MHz) or defined by users in dts.
> > Dw-i3c-master should not hard-code the initial speed to be
> > I3C_BUS_TYP_I3C_SCL_RATE (12.5MHz) And because of Synopsys's I3C
> > controller limit (hcnt/lcnt register
> > length) and core-clk provided, there is a limit to bus speed, too.
> > For example, when core-clk is 250 MHz, the bus speed cannot be lowered
> > below 1MHz.
> >
> > Tested: tested with an i3c sensor and captured with a logic analyzer.
> 
> This is already in 6.12.0, so no need to do anything there. Looks good to me.
> 
> Reviewed-by: Pavel Machek <[email protected]>
> 
> I'll apply it if it passes testing (and there are no other comments).

Thanks, I applied with your Reviewed-by tag.
> 
> Best regards,
>                                                                 Pavel
> 

Best regards,
  Nobuhiro