From: Alex Hung <[email protected]>
[WHAT]
Add KUnit tests for amdgpu_dm_plane_get_gfx6_tile_idx(),
amdgpu_dm_plane_calc_gfx7_tile_split() and
amdgpu_dm_plane_get_gfx7_macro_tile_idx() covering the per-family tile
mode index selection, the tile split derived from the sample split
factor with its 256 byte and memory row size clamps, and the macro tile
index capped by the tile split.
Assisted-by: Copilot:Claude-Opus-5
Reviewed-by: Bhawanpreet Lakha <[email protected]>
Signed-off-by: Alex Hung <[email protected]>
Signed-off-by: Ivan Lipski <[email protected]>
---
.../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 18 +++--
.../amd/display/amdgpu_dm/amdgpu_dm_plane.h | 5 ++
.../amdgpu_dm/tests/amdgpu_dm_plane_test.c | 81 +++++++++++++++++++
3 files changed, 97 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
index 824ef3ce5de0a..d6b80c380db85 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
@@ -504,9 +504,9 @@ static void amdgpu_dm_plane_add_gfx10_1_modifiers(const struct amdgpu_device *ad
* present at specific indices.
* See SiLib::HwlSetupTileInfo() and CiLib::HwlSetupTileInfo() in addrlib.
*/
-static u32 amdgpu_dm_plane_get_gfx6_tile_idx(const struct amdgpu_device *adev,
- const u32 bpp,
- const enum array_mode_values arr)
+STATIC_IFN_KUNIT u32 amdgpu_dm_plane_get_gfx6_tile_idx(const struct amdgpu_device *adev,
+ const u32 bpp,
+ const enum array_mode_values arr)
{
/* Assume that the microtile mode is DISPLAY. */
@@ -527,6 +527,7 @@ static u32 amdgpu_dm_plane_get_gfx6_tile_idx(const struct amdgpu_device *adev,
return 12;
}
}
+EXPORT_IF_KUNIT(amdgpu_dm_plane_get_gfx6_tile_idx);
/**
* amdgpu_dm_plane_calc_gfx7_tile_split() - Calculate tile split on GFX7-8
@@ -542,9 +543,9 @@ static u32 amdgpu_dm_plane_get_gfx6_tile_idx(const struct amdgpu_device *adev,
* can be calculated. The TILE_SPLIT field is only used for the depth micro tile mode.
* See CiLib::HwlComputeMacroModeIndex() in addrlib.
*/
-static u32 amdgpu_dm_plane_calc_gfx7_tile_split(const struct amdgpu_device *adev,
- const u32 bpp,
- const u32 gb_tile_mode)
+STATIC_IFN_KUNIT u32 amdgpu_dm_plane_calc_gfx7_tile_split(const struct amdgpu_device *adev,
+ const u32 bpp,
+ const u32 gb_tile_mode)
{
/* Assume 2D_TILED_THIN1 mode with non-DEPTH microtiles */
const u32 sample_split = (gb_tile_mode >> 25) & 0x3;
@@ -557,6 +558,7 @@ static u32 amdgpu_dm_plane_calc_gfx7_tile_split(const struct amdgpu_device *adev
256,
adev->gfx.config.mem_row_size_in_kb * 1024);
}
+EXPORT_IF_KUNIT(amdgpu_dm_plane_calc_gfx7_tile_split);
/**
* amdgpu_dm_plane_get_gfx7_macro_tile_idx() - Get macro tile mode index on GFX7-8
@@ -570,7 +572,8 @@ static u32 amdgpu_dm_plane_calc_gfx7_tile_split(const struct amdgpu_device *adev
* present at specific indices.
* See CiLib::HwlComputeMacroModeIndex() in addrlib.
*/
-static u32 amdgpu_dm_plane_get_gfx7_macro_tile_idx(const u32 bpp, const u32 tile_split_bytes)
+STATIC_IFN_KUNIT u32 amdgpu_dm_plane_get_gfx7_macro_tile_idx(const u32 bpp,
+ const u32 tile_split_bytes)
{
const u32 thickness = 1;
const u32 tile_size_pixels = 8 * 8;
@@ -582,6 +585,7 @@ static u32 amdgpu_dm_plane_get_gfx7_macro_tile_idx(const u32 bpp, const u32 tile
return macro_tile_idx;
}
+EXPORT_IF_KUNIT(amdgpu_dm_plane_get_gfx7_macro_tile_idx);
/**
* amdgpu_dm_plane_calc_gfx6_mod() - Calculate a DRM format modifier for GFX6-8
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h
index 092ade738ce98..7c5d0a7dadb1d 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h
@@ -125,5 +125,10 @@ void amdgpu_dm_plane_add_modifier_dedup(uint64_t **mods, uint64_t *size,
uint64_t *cap, uint64_t mod);
int amdgpu_dm_plane_fill_gfx6_tiling_info_from_modifier(struct dc_tiling_info *tiling_info,
uint64_t modifier);
+u32 amdgpu_dm_plane_get_gfx6_tile_idx(const struct amdgpu_device *adev, const u32 bpp,
+ const enum array_mode_values arr);
+u32 amdgpu_dm_plane_calc_gfx7_tile_split(const struct amdgpu_device *adev, const u32 bpp,
+ const u32 gb_tile_mode);
+u32 amdgpu_dm_plane_get_gfx7_macro_tile_idx(const u32 bpp, const u32 tile_split_bytes);
#endif
#endif
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_plane_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_plane_test.c
index aaec65d7431ce..420b053d2e3dc 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_plane_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_plane_test.c
@@ -3277,6 +3277,81 @@ static void dm_test_fill_gfx6_tiling_info_2d(struct kunit *test)
KUNIT_EXPECT_EQ(test, tiling_info.gfx8.num_banks, 2U);
}
+/**
+ * dm_test_get_gfx6_tile_idx() - Verify GFX6-8 tile mode index selection.
+ * @test: KUnit test context.
+ *
+ * Verify if the micro tiled mode maps to a fixed index, GFX7+ uses a single
+ * macro tiled index, and GFX6 selects the index from the bits per pixel.
+ */
+static void dm_test_get_gfx6_tile_idx(struct kunit *test)
+{
+ struct amdgpu_device *adev;
+
+ adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
+ KUNIT_ASSERT_NOT_NULL(test, adev);
+
+ adev->family = AMDGPU_FAMILY_VI;
+ KUNIT_EXPECT_EQ(test,
+ amdgpu_dm_plane_get_gfx6_tile_idx(adev, 32, DC_ARRAY_1D_TILED_THIN1),
+ 9U);
+ KUNIT_EXPECT_EQ(test,
+ amdgpu_dm_plane_get_gfx6_tile_idx(adev, 32, DC_ARRAY_2D_TILED_THIN1),
+ 10U);
+
+ adev->family = AMDGPU_FAMILY_SI;
+ KUNIT_EXPECT_EQ(test,
+ amdgpu_dm_plane_get_gfx6_tile_idx(adev, 8, DC_ARRAY_2D_TILED_THIN1),
+ 10U);
+ KUNIT_EXPECT_EQ(test,
+ amdgpu_dm_plane_get_gfx6_tile_idx(adev, 16, DC_ARRAY_2D_TILED_THIN1),
+ 11U);
+ KUNIT_EXPECT_EQ(test,
+ amdgpu_dm_plane_get_gfx6_tile_idx(adev, 32, DC_ARRAY_2D_TILED_THIN1),
+ 12U);
+}
+
+/**
+ * dm_test_calc_gfx7_tile_split() - Verify GFX7-8 tile split calculation.
+ * @test: KUnit test context.
+ *
+ * Verify if the tile split is derived from the sample split factor and clamped
+ * to the 256 byte minimum and the memory row size maximum.
+ */
+static void dm_test_calc_gfx7_tile_split(struct kunit *test)
+{
+ struct amdgpu_device *adev;
+
+ adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
+ KUNIT_ASSERT_NOT_NULL(test, adev);
+
+ adev->gfx.config.mem_row_size_in_kb = 4;
+
+ /* 8 bpp gives 64 bytes, clamped up to the 256 byte minimum. */
+ KUNIT_EXPECT_EQ(test, amdgpu_dm_plane_calc_gfx7_tile_split(adev, 8, 0u << 25), 256U);
+ /* 32 bpp with a sample split factor of 2. */
+ KUNIT_EXPECT_EQ(test, amdgpu_dm_plane_calc_gfx7_tile_split(adev, 32, 1u << 25), 512U);
+
+ /* 64 bpp with a sample split factor of 8, clamped to the memory row size. */
+ adev->gfx.config.mem_row_size_in_kb = 1;
+ KUNIT_EXPECT_EQ(test, amdgpu_dm_plane_calc_gfx7_tile_split(adev, 64, 3u << 25), 1024U);
+}
+
+/**
+ * dm_test_get_gfx7_macro_tile_idx() - Verify GFX7-8 macro tile index selection.
+ * @test: KUnit test context.
+ *
+ * Verify if the macro tile index is the log2 of the tile size in 64 byte units,
+ * clamped to the tile split.
+ */
+static void dm_test_get_gfx7_macro_tile_idx(struct kunit *test)
+{
+ KUNIT_EXPECT_EQ(test, amdgpu_dm_plane_get_gfx7_macro_tile_idx(8, 1024), 0U);
+ KUNIT_EXPECT_EQ(test, amdgpu_dm_plane_get_gfx7_macro_tile_idx(32, 1024), 2U);
+ /* 64 bpp needs 512 bytes but the tile split caps it at 256. */
+ KUNIT_EXPECT_EQ(test, amdgpu_dm_plane_get_gfx7_macro_tile_idx(64, 256), 2U);
+}
+
static struct kunit_case amdgpu_dm_plane_test_cases[] = {
/* amdgpu_dm_plane_is_video_format() */
KUNIT_CASE(dm_test_plane_is_video_format_known_video),
@@ -3371,6 +3446,12 @@ static struct kunit_case amdgpu_dm_plane_test_cases[] = {
KUNIT_CASE(dm_test_fill_gfx6_tiling_info_rejects),
KUNIT_CASE(dm_test_fill_gfx6_tiling_info_1d),
KUNIT_CASE(dm_test_fill_gfx6_tiling_info_2d),
+ /* amdgpu_dm_plane_get_gfx6_tile_idx() */
+ KUNIT_CASE(dm_test_get_gfx6_tile_idx),
+ /* amdgpu_dm_plane_calc_gfx7_tile_split() */
+ KUNIT_CASE(dm_test_calc_gfx7_tile_split),
+ /* amdgpu_dm_plane_get_gfx7_macro_tile_idx() */
+ KUNIT_CASE(dm_test_get_gfx7_macro_tile_idx),
/* amdgpu_dm_plane_fill_gfx9_tiling_info_from_device() */
KUNIT_CASE(dm_test_fill_gfx9_tiling_info_from_device_pre_10_3),
KUNIT_CASE(dm_test_fill_gfx9_tiling_info_from_device_10_3_plus),
--
2.43.0
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