[PATCH i-g-t 0/3] gem_wsim: fix batch premature completion
Marcin Bernatowicz <[email protected]> Fri, 31 Jul 2026 16:18:03 +0200
| Newsgroups | org.freedesktop.lists.igt-dev |
|---|---|
| Message-ID | <[email protected]> |
Fixes observed verification failure under looped runs:
gem_wsim -w "1.RCS.5000.0.0,1.BCS.5000.0.0,1.CCS.5000.0.1,1.VCS.5000.0.0"
-V -r 4000
CRITICAL: Failed assertion:
w->duration.requested_ticks <= ~w->xe.data->spin.ticks_delta
CRITICAL: error: 96000 > 2
V1 attempted to fix the issue by initializing ticks_delta to ~0u in
xe_spin and resetting it from the host before each fixed-duration
submission in gem_wsim.
V2 fix (suggested by Zbigniew): write sentinel 0 to ticks_delta and use
MI_SEMAPHORE_WAIT to confirm it's in memory before entering the loop.
This is a self-contained GPU-side fix - no host-side reset per submission
needed. Also switches from inverted ticks_delta (STOREINV + ~ctx_ticks)
to direct elapsed (STORE + MAD_LT_IDD + ctx_ticks) for readability.
V1 -> V2:
- Replace host-side ticks_delta reset with GPU-side SDW+SEMAPHORE_WAIT
- Switch from inverted to direct elapsed ticks logic
- Remove ineffective pad loop between SRM and COND_BBE
- Add xe_sriov_scheduling.c fix for the same ticks_delta check
Marcin Bernatowicz (3):
lib/xe/xe_spin: fix premature batch exit on BO resubmission
benchmarks/gem_wsim: fix ticks_delta assertion for non-inverted logic
tests/xe_sriov_scheduling: fix ticks_delta check for non-inverted
logic
benchmarks/gem_wsim.c | 2 +-
lib/xe/xe_spin.c | 31 +++++++++++++++++--------------
tests/intel/xe_sriov_scheduling.c | 2 +-
3 files changed, 19 insertions(+), 16 deletions(-)
--
2.43.0