RE: [PATCH 06/14] drm/i915/dp: Add a wrapper to check frl/tmds downstream constraints

> Subject: [PATCH 06/14] drm/i915/dp: Add a wrapper to check frl/tmds
> downstream constraints
>=20
> Add a wrapper function to check dp_downstream clock/bandwidth constraints=
.
> Based on whether the sink supports FRL/TMDS the wrapper calls the
> appropriate FRL/TMDS functions.
>=20
> Signed-off-by: Ankit Nautiyal <[email protected]>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 36 ++++++++++++++++++-------
>  1 file changed, 26 insertions(+), 10 deletions(-)
>=20
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index eb76e6b6d616..6bf42128a81d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1206,6 +1206,28 @@ intel_dp_frl_bw_valid(struct intel_dp *intel_dp, i=
nt
> target_clock,
>  	return MODE_OK;
>  }
>=20
> +static bool
> +intel_dp_pcon_sink_support_frl(struct intel_dp *intel_dp) {
> +	return intel_dp->dfp.pcon_max_frl_bw &&
> +		intel_dp_hdmi_sink_max_frl(intel_dp);
> +}
> +
> +static enum drm_mode_status
> +intel_dp_hdmi_bw_valid(struct intel_dp *intel_dp,
> +		       int target_clock, int bpc,
> +		       enum intel_output_format sink_format,
> +		       bool respect_downstream_limits) {
> +	if (intel_dp_pcon_sink_support_frl(intel_dp))
> +		return intel_dp_frl_bw_valid(intel_dp, target_clock, bpc,
> +					     sink_format,
> +					     respect_downstream_limits);
> +
> +	return intel_dp_tmds_clock_valid(intel_dp, target_clock, bpc,
> sink_format,
> +					 respect_downstream_limits);
> +}
> +
>  static enum drm_mode_status
>  intel_dp_mode_valid_downstream(struct intel_connector *connector,
>  			       const struct drm_display_mode *mode, @@ -
> 1213,20 +1235,14 @@ intel_dp_mode_valid_downstream(struct
> intel_connector *connector,
>  			       enum intel_output_format sink_format)  {
>  	struct intel_dp *intel_dp =3D intel_attached_dp(connector);
> +	int bpc =3D 8; /* Assume 8bpc for the DP++/HDMI/DVI TMDS/FRL bw
> check */
>=20
> -	/* If PCON supports FRL MODE, check FRL bandwidth constraints */
> -	if (intel_dp->dfp.pcon_max_frl_bw &&
> intel_dp_hdmi_sink_max_frl(intel_dp)) {
> -		/* Assume 8bpc for the HDMI2.1 FRL BW check */
> -		return intel_dp_frl_bw_valid(intel_dp, target_clock, 8,
> sink_format, true);
> -	}
> -
> -	if (intel_dp->dfp.max_dotclock &&
> +	if (!intel_dp_hdmi_sink_max_frl(intel_dp) &&
> +	    intel_dp->dfp.max_dotclock &&
>  	    target_clock > intel_dp->dfp.max_dotclock)
>  		return MODE_CLOCK_HIGH;

Does this change maybe belong inside dp_tmds_clock_valid ?

Regards,
Suraj Kandpal

>=20
> -	/* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
> -	return intel_dp_tmds_clock_valid(intel_dp, target_clock,
> -					 8, sink_format, true);
> +	return intel_dp_hdmi_bw_valid(intel_dp, target_clock, bpc,
> +sink_format, true);
>  }
>=20
>  static enum drm_mode_status
> --
> 2.50.1