[PATCH] drm/xe/xe_debugfs: Expose G-State and PCIe link state debugfs for CRI

Expose G-State and PCIe link state through debugfs for CRI. The PMT
offsets for these metrics are identical to those used on BMG, so
remove the BMG_ prefix from the corresponding offset macros to make
them platform-agnostic.

Also enable these debugfs support on all dGPU platforms from BMG onward.

Signed-off-by: Karthik Poosa <[email protected]>
---
 drivers/gpu/drm/xe/regs/xe_pmt.h | 20 ++++++++++----------
 drivers/gpu/drm/xe/xe_debugfs.c  | 20 ++++++++++----------
 2 files changed, 20 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/xe/regs/xe_pmt.h b/drivers/gpu/drm/xe/regs/xe_pmt.h
index a62ab05c6b4c..54df1c8a9f8f 100644
--- a/drivers/gpu/drm/xe/regs/xe_pmt.h
+++ b/drivers/gpu/drm/xe/regs/xe_pmt.h
@@ -20,15 +20,15 @@
 #define BMG_TELEMETRY_BASE_OFFSET	0xE0000
 #define BMG_TELEMETRY_OFFSET		(SOC_BASE + BMG_TELEMETRY_BASE_OFFSET)
 
-#define BMG_MODS_RESIDENCY_OFFSET		(0x4D0)
-#define BMG_G2_RESIDENCY_OFFSET		(0x530)
-#define BMG_G6_RESIDENCY_OFFSET		(0x538)
-#define BMG_G7_RESIDENCY_OFFSET		(0x4B0)
-#define BMG_G8_RESIDENCY_OFFSET		(0x540)
-#define BMG_G10_RESIDENCY_OFFSET		(0x548)
-
-#define BMG_PCIE_LINK_L0_RESIDENCY_OFFSET	(0x570)
-#define BMG_PCIE_LINK_L1_RESIDENCY_OFFSET	(0x578)
-#define BMG_PCIE_LINK_L1_2_RESIDENCY_OFFSET	(0x580)
+#define MODS_RESIDENCY_OFFSET		(0x4D0)
+#define G2_RESIDENCY_OFFSET		(0x530)
+#define G6_RESIDENCY_OFFSET		(0x538)
+#define G7_RESIDENCY_OFFSET		(0x4B0)
+#define G8_RESIDENCY_OFFSET		(0x540)
+#define G10_RESIDENCY_OFFSET		(0x548)
+
+#define PCIE_LINK_L0_RESIDENCY_OFFSET	(0x570)
+#define PCIE_LINK_L1_RESIDENCY_OFFSET	(0x578)
+#define PCIE_LINK_L1_2_RESIDENCY_OFFSET	(0x580)
 
 #endif
diff --git a/drivers/gpu/drm/xe/xe_debugfs.c b/drivers/gpu/drm/xe/xe_debugfs.c
index 8de78cd0aa03..9cc104046756 100644
--- a/drivers/gpu/drm/xe/xe_debugfs.c
+++ b/drivers/gpu/drm/xe/xe_debugfs.c
@@ -241,12 +241,12 @@ static int dgfx_pkg_residencies_show(struct seq_file *m, void *data)
 		u32 offset;
 		const char *name;
 	} residencies[] = {
-		{BMG_G2_RESIDENCY_OFFSET, "Package G2"},
-		{BMG_G6_RESIDENCY_OFFSET, "Package G6"},
-		{BMG_G7_RESIDENCY_OFFSET, "Package G7"},
-		{BMG_G8_RESIDENCY_OFFSET, "Package G8"},
-		{BMG_G10_RESIDENCY_OFFSET, "Package G10"},
-		{BMG_MODS_RESIDENCY_OFFSET, "Package ModS"}
+		{G2_RESIDENCY_OFFSET, "Package G2"},
+		{G6_RESIDENCY_OFFSET, "Package G6"},
+		{G7_RESIDENCY_OFFSET, "Package G7"},
+		{G8_RESIDENCY_OFFSET, "Package G8"},
+		{G10_RESIDENCY_OFFSET, "Package G10"},
+		{MODS_RESIDENCY_OFFSET, "Package ModS"}
 	};
 
 	for (int i = 0; i < ARRAY_SIZE(residencies); i++)
@@ -270,9 +270,9 @@ static int dgfx_pcie_link_residencies_show(struct seq_file *m, void *data)
 		u32 offset;
 		const char *name;
 	} residencies[] = {
-		{BMG_PCIE_LINK_L0_RESIDENCY_OFFSET, "PCIE LINK L0 RESIDENCY"},
-		{BMG_PCIE_LINK_L1_RESIDENCY_OFFSET, "PCIE LINK L1 RESIDENCY"},
-		{BMG_PCIE_LINK_L1_2_RESIDENCY_OFFSET, "PCIE LINK L1.2 RESIDENCY"}
+		{PCIE_LINK_L0_RESIDENCY_OFFSET, "PCIE LINK L0 RESIDENCY"},
+		{PCIE_LINK_L1_RESIDENCY_OFFSET, "PCIE LINK L1 RESIDENCY"},
+		{PCIE_LINK_L1_2_RESIDENCY_OFFSET, "PCIE LINK L1.2 RESIDENCY"}
 	};
 
 	for (int i = 0; i < ARRAY_SIZE(residencies); i++)
@@ -695,7 +695,7 @@ void xe_debugfs_register(struct xe_device *xe)
 				 ARRAY_SIZE(debugfs_list),
 				 root, minor);
 
-	if (xe->info.platform == XE_BATTLEMAGE && !IS_SRIOV_VF(xe)) {
+	if (IS_DGFX(xe) && xe->info.platform >= XE_BATTLEMAGE && !IS_SRIOV_VF(xe)) {
 		drm_debugfs_create_files(debugfs_residencies,
 					 ARRAY_SIZE(debugfs_residencies),
 					 root, minor);
-- 
2.25.1