[PATCH 0/2] clk: spacemit: fix PLL init and add K3 1.8 GHz rates

The PLL and PLLA init callbacks leave a PLL gated off once they
reprogram an unmatched firmware configuration. Re-enable the PLL to
complete the disable-update-enable sequence and propagate any lock
timeout to clock registration. Apply this to both the K1 PLL and K3
PLLA implementations.

The K3 SoC may not remain stable when its A100 CPU clusters operate
persistently at 2 GHz. Updated U-Boot firmware therefore configures
their C2 and C3 clock domains at 1.8 GHz during early initialization.
PLL5 feeds C2 and PLL8 feeds C3, so add 1.8 GHz as the default
rate-table entry for both PLLs.

The related U-Boot change is available at:
https://github.com/spacemit-com/uboot-2022.10/commit/fb95cf3d848b771c61b5a1b3e5cbbee223faf352

Signed-off-by: Troy Mitchell <[email protected]>
---
Troy Mitchell (2):
      clk: spacemit: re-enable PLLs after init
      clk: spacemit: k3: add 1.8 GHz PLL5 and PLL8 rates

 drivers/clk/spacemit/ccu-k3.c  | 2 ++
 drivers/clk/spacemit/ccu_pll.c | 4 ++--
 2 files changed, 4 insertions(+), 2 deletions(-)
---
base-commit: 1590cf0329716306e948a8fc29f1d3ee87d3989f
change-id: 20260802-k3-pll5-pll8-1800mhz-c81875a0a944

Best regards,
--  
Troy Mitchell <[email protected]>


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