Re: [PATCH 1/2] clk: spacemit: re-enable PLLs after init

On Tue, Aug 04, 2026 at 12:02:55AM -0700, Troy Mitchell wrote:
> The PLL and PLLA init callbacks gate off and reprogram a PLL when its
> firmware configuration is absent from the rate table. However, they
> leave the PLL gated off after updating the registers.

I don't think this patch makes sense.

If this PLL is essential for some components of the systems to work,
there's no chance to re-program it safely after the kernel gets started,
since all the PLLs in K1 and K3 are specified as CLK_SET_RATE_GATE.

If the essential clocks could be re-parented glitchlessly, registering
a notifier and re-parenting it before the PLL disables might be a
solution. In this case, we need to delay the operation in
ccu_pll*_init() until clock registration fully completes.

Otherwise, re-enabling the PLL seems totally extra here, they could be
enabled on the fly when it's going to be used.

> Re-enable the PLL to complete the sequence and propagate any lock
> timeout to clock registration.

Regards,
Yao Zi

> Fixes: 1b72c59db0ad ("clk: spacemit: Add clock support for SpacemiT K1 SoC")
> Fixes: 3a086236c600 ("clk: spacemit: ccu_pll: add plla type clock")
> Signed-off-by: Troy Mitchell <[email protected]>

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