[MODERATED] Re: [PATCH v1 6/9] PERFv1 5

On Mon, Feb 04, 2019 at 05:14:07PM -0800, speck for Andi Kleen wrote:
> From: Andi Kleen <[email protected]>
> Subject:  x86/pmu/intel: Add global option for enable all
>  counters
> 
> Add a global setting to allow to disable RTM when counter 3
> is needed for some perf event group. Otherwise RTM will
> not be impacted.
> 
> This allows existing programs that want to use groups
> with all four counters to run without changes.
> 
> This patch sets the default to TSX enabled, but
> that could be easily changed.
> 
> The trade offs for setting the option default are:
> 
> Using 4 (or 8 with HT off) events in perf versus
> allowing RTM usage while perf is active.
> 
> - Existing programs that use perf groups with 4 counters
> may not retrieve perfmon data anymore. Perf usages
> that use less than four (or 7 with HT off) counters
> are not impacted. Perf usages that don't use group
> will still work, but will see increase multiplexing.
> 
> - TSX programs should not functionally break from
> forcing RTM to abort because they always need a valid
> fall back path. However they will see significantly
> lower performance if they rely on TSX for performance
> (all RTM transactions will run and only abort at the end),
> potentially slowing them down so much that it is
> equivalent to functional breakage.

So you know tglx and me have been arguing for the opposite default. This
will 'silently' break stuff that relies on having the counters present
-- and there are people who do indeed rely on that.

At the same time; by default there are no (with the possible exception
of the NMI watchdog) users of the PMU, and I don't think TSX is in fact
used by default either.

This means that only people that explicitly use TSX and perf at the same
time are impacted with that default, and the rest will actually work.