[MODERATED] Re: [PATCH 1/9] TAA 1

On Thu, Oct 24, 2019 at 10:22:57AM -0500, speck for Josh Poimboeuf wrote:
> This should clarify that not *all* TAA-vulnerable CPUs will get
> IA32_TSX_CTRL, instead only the ones which aren't also vulnerable to
> MDS.

Added:

"The CPUs which get this new MSR after a microcode upgrade are the ones
which do not set MSR_IA32_ARCH_CAPABILITIES.MDS_NO (bit 5) because those
CPUs have CPUID.MD_CLEAR, i.e., the VERW implementation which clears all
CPU buffers takes care of the TAA case as well."

Hopefully that makes it more clear.

> > The other TSX sub-feature, Hardware Lock Elision (HLE), is
> > unconditionally disabled
> 
> ... by the new microcode ...
> 
> > but still enumerated as present by
> > CPUID(EAX=7).EBX{bit4}.
> 
> ... unless disabled by bit 1 of IA32_TSX_CTRL_MSR.

Changed it to:

"The other TSX sub-feature, Hardware Lock Elision (HLE), is
unconditionally disabled by the new microcode but still enumerated
as present by CPUID(EAX=7).EBX{bit4}, unless disabled by
IA32_TSX_CTRL_MSR[1] - TSX_CTRL_CPUID_CLEAR."

Thx.

-- 
Regards/Gruss,
    Boris.

SUSE Software Solutions Germany GmbH, GF: Felix Imendörffer, HRB 36809, AG Nürnberg
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