Re: [PATCH 04/12] clk: qcom: ipq-cmn-pll: Add NSS clock support

On 7/24/26 5:00 PM, Luo Jie wrote:
> The NSS (network subsystem) clock is derived from the CMN PLL output
> divided by 2 and then further divided by a configurable 6-bit divider
> with a valid range of 8-63.
> 
> Signed-off-by: Luo Jie <[email protected]>
> ---

This looks very similar to clk-regmap-divider.c (or at least to
the generic clk-divider.c implementation).

[...]

>  	/* Register the fixed rate output clocks. */
>  	for (i = 0; i < num_clks; i++) {
> -		struct clk_parent_data pdata = { .hw = cmn_pll_hw };
> +		if (fixed_clk[i].rate) {
> +			struct clk_parent_data pdata = { .hw = cmn_pll_hw };
> +
> +			hw = devm_clk_hw_register_fixed_rate_parent_data(dev,
> +									 fixed_clk[i].name,
> +									 &pdata, 0,
> +									 fixed_clk[i].rate);
> +		} else if (!strcmp(fixed_clk[i].name, "nss")) {
> +			hw = ipq_cmn_pll_nss_register(pdev, cmn_pll->regmap,
> +						      cmn_pll_hw);

Huge "no", this must be a compile-time constant and not rely on
some funky detection.

Konrad