Re: [PATCH 09/12] clk: qcom: ipq-cmn-pll: Add clock gate support for fixed clocks

On 7/24/26 5:00 PM, Luo Jie wrote:
> Some CMN PLL output clocks require a hardware gate in addition to a
> fixed rate. The gate control bits reside in the register
> CMN_PLL_OUTPUT_RELATED_1 (0x79c). Each such clock is registered as a
> composite clock combining a clk_fixed_rate provider with a clk_gate.

Would toggling this register in .enable/.disable not be good enough?
Do we need to register a separate gate?

Konrad