[PATCH v3 1/6] dt-bindings: clock: agilex5: Add USB3.1 reference clock ID

Adrian Ng Ho Yin <[email protected]>
Newsgroups org.kernel.vger.linux-clk,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-kernel,org.kernel.vger.linux-usb
Message-ID <9b583ba4a5ca48d07854b7d005b43b41fefa7fa3.1786518803.git.adrian.ho.yin.ng@altera.com>
The Synopsys DWC3 USB3.1 controller requires two separately named
clocks: a suspend clock and a reference clock. The existing binding
only exposes AGILEX5_USB31_SUSPEND_CLK. Add AGILEX5_USB31_REF_CLK
to allow DT nodes to reference the reference clock by its own ID,
and update AGILEX5_NUM_CLKS accordingly.

Signed-off-by: Adrian Ng Ho Yin <[email protected]>
---
 include/dt-bindings/clock/intel,agilex5-clkmgr.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/include/dt-bindings/clock/intel,agilex5-clkmgr.h b/include/dt-bindings/clock/intel,agilex5-clkmgr.h
index 2f3a23b31c5c..196c0bad3e52 100644
--- a/include/dt-bindings/clock/intel,agilex5-clkmgr.h
+++ b/include/dt-bindings/clock/intel,agilex5-clkmgr.h
@@ -95,6 +95,7 @@
 #define AGILEX5_SOFTPHY_REG_PCLK	79
 #define AGILEX5_SOFTPHY_PHY_CLK		80
 #define AGILEX5_SOFTPHY_CTRL_CLK	81
-#define AGILEX5_NUM_CLKS		82
+#define AGILEX5_USB31_REF_CLK		82
+#define AGILEX5_NUM_CLKS		83
 
 #endif	/* __DT_BINDINGS_INTEL_AGILEX5_CLKMGR_H */
-- 
2.49.GIT
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