[PATCH v3 2/6] clk: socfpga: agilex5: add usb3.1 reference clock

The Agilex5 DWC3 controller exposes separate ref and suspend clock
inputs. On this SoC both inputs are driven by the same hardware source,
usb31_suspend_clk.

Register usb31_ref_clk as a fixed-factor 1:1 child of usb31_suspend_clk
so the DWC3 driver can request each input by name. A fixed-factor clock
is used instead of a gate entry because agilex5_register_gate() assigns
the gate register unconditionally; a zero gate_reg maps to the clock
manager base address, which would corrupt the boot PLL register on
clk_enable().

Signed-off-by: Adrian Ng Ho Yin <[email protected]>
---
 drivers/clk/socfpga/clk-agilex5.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/clk/socfpga/clk-agilex5.c b/drivers/clk/socfpga/clk-agilex5.c
index f7f0ad884f64..af3009ddc6ab 100644
--- a/drivers/clk/socfpga/clk-agilex5.c
+++ b/drivers/clk/socfpga/clk-agilex5.c
@@ -526,6 +526,21 @@ static int agilex5_clkmgr_init(struct platform_device *pdev)
 	agilex5_clk_register_gate(agilex5_gate_clks,
 				  ARRAY_SIZE(agilex5_gate_clks), clk_data);
 
+	/*
+	 * usb31_ref_clk is a 1:1 alias of usb31_suspend_clk. The DWC3
+	 * controller uses the same source for both its suspend and reference
+	 * clock inputs on this SoC. Register it as a fixed-factor (passthrough)
+	 * clock so that enabling it propagates to the parent gate without
+	 * touching any gate register of its own.
+	 */
+	clk_data->clk_data.hws[AGILEX5_USB31_REF_CLK] =
+		devm_clk_hw_register_fixed_factor(dev, "usb31_ref_clk",
+						  "usb31_suspend_clk", 0, 1, 1);
+	if (IS_ERR(clk_data->clk_data.hws[AGILEX5_USB31_REF_CLK]))
+		return dev_err_probe(dev,
+			PTR_ERR(clk_data->clk_data.hws[AGILEX5_USB31_REF_CLK]),
+			"failed to register clock usb31_ref_clk\n");
+
 	of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &clk_data->clk_data);
 	return 0;
 }
-- 
2.49.GIT