Re: [PATCH v2 8/9] clk: renesas: r9a08g046: Add MIPI DSI and LCDC clock/reset entries
Geert Uytterhoeven <[email protected]>
| Newsgroups | org.kernel.vger.linux-clk,org.kernel.vger.linux-kernel,org.kernel.vger.linux-renesas-soc |
|---|---|
| Message-ID | <CAMuHMdWbg3cT4onaxj8Bz+MZyW+WBHG-q6FU7hSKQga2yXDi5g@mail.gmail.com> |
On Tue, 11 Aug 2026 at 20:27, Biju <[email protected]> wrote: > From: Biju Das <[email protected]> > > Add clock and reset entries for the MIPI DSI and LCDC peripherals on the > RZ/G3L (R9A08G046) SoC. > > Signed-off-by: Biju Das <[email protected]> > --- > v1->v2: > * Replaced M2_DIV7->.m2_div7 as it is internal clock > * Added DEF_G3L_LVDS_DIV for fixed factor clock with 4:7 duty cycle. > * Prefix mipi_ added for all DSI clks. > * Fixed commit header /r9a08g046-cpg/r9a08g046/ > * Sorted DSI entries. Reviewed-by: Geert Uytterhoeven <[email protected]> i.e. will queue in renesas-clk for v7.4. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected] In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds