[PATCH v7 7/8] cxl/pci: Split BI capability probe from setup
Davidlohr Bueso <[email protected]> Tue, 28 Jul 2026 07:41:35 -0700
| Newsgroups | org.kernel.vger.linux-cxl |
|---|---|
| Message-ID | <[email protected]> |
Decouple the topology read-only capability verification phase from cxl_bi_setup() into cxl_bi_probe_capable(), recording the result in cxlds->bi_capable. This allows further dealing with auto-committed BI hdm decoders; having such knowledge upon decoder enumeration time. No functional change intended. Signed-off-by: Davidlohr Bueso <[email protected]> --- drivers/cxl/core/pci.c | 39 ++++++++++++++++++++++++++++----------- drivers/cxl/cxl.h | 1 + drivers/cxl/port.c | 1 + include/cxl/cxl.h | 2 ++ 4 files changed, 32 insertions(+), 11 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index a87c2ad9ac53..554058ccb1e9 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -1290,35 +1290,38 @@ static int cxl_bi_enable_path(struct cxl_dev_state *cxlds, return rc; } -int cxl_bi_setup(struct cxl_port *endpoint) +/* + * Verify the device and every component in the path up to the root + * are BI capable. + */ +void cxl_bi_probe_capable(struct cxl_port *endpoint) { struct cxl_memdev *cxlmd = to_cxl_memdev(endpoint->uport_dev); struct cxl_dev_state *cxlds = cxlmd->cxlds; - struct cxl_dport *dport = endpoint->parent_dport; struct cxl_dport *dport_iter; struct cxl_port *port_iter; - int rc; + + cxlds->bi_capable = false; if (!dev_is_pci(cxlds->dev)) - return 0; + return; /* BI is VH-only */ if (cxlds->rcd) - return 0; + return; if (!cxl_is_bi_capable(to_pci_dev(cxlds->dev), endpoint->regs.bi_decoder)) - return 0; + return; - /* walkup the topology twice, first to check, then to enable */ - port_iter = dport->port; - dport_iter = dport; + dport_iter = endpoint->parent_dport; + port_iter = dport_iter->port; while (!is_cxl_root(port_iter)) { /* check rp, dsp */ if (!cxl_is_bi_capable(to_pci_dev(dport_iter->dport_dev), dport_iter->regs.bi_decoder)) { dev_dbg(cxlds->dev, "BI not supported by topology\n"); - return 0; + return; } /* check usp */ @@ -1328,13 +1331,27 @@ int cxl_bi_setup(struct cxl_port *endpoint) !cxl_is_bi_capable(to_pci_dev(port_iter->uport_dev), port_iter->regs.bi_rt)) { dev_dbg(cxlds->dev, "BI not supported by USP\n"); - return 0; + return; } dport_iter = port_iter->parent_dport; port_iter = dport_iter->port; } + cxlds->bi_capable = true; +} +EXPORT_SYMBOL_NS_GPL(cxl_bi_probe_capable, "CXL"); + +int cxl_bi_setup(struct cxl_port *endpoint) +{ + struct cxl_memdev *cxlmd = to_cxl_memdev(endpoint->uport_dev); + struct cxl_dev_state *cxlds = cxlmd->cxlds; + struct cxl_dport *dport = endpoint->parent_dport; + int rc; + + if (!cxlds->bi_capable) + return 0; + rc = cxl_bi_enable_path(cxlds, dport->port, dport); if (rc) return rc; diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index ca7051641c47..e10d642684e1 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -963,6 +963,7 @@ void cxl_coordinates_combine(struct access_coordinate *out, struct access_coordinate *c2); bool cxl_endpoint_decoder_reset_detected(struct cxl_port *port); +void cxl_bi_probe_capable(struct cxl_port *endpoint); int cxl_bi_setup(struct cxl_port *endpoint); struct cxl_dport *devm_cxl_add_dport_by_dev(struct cxl_port *port, struct device *dport_dev); diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c index 22bd4254ba8d..ab3317fc1388 100644 --- a/drivers/cxl/port.c +++ b/drivers/cxl/port.c @@ -170,6 +170,7 @@ static int cxl_endpoint_port_probe(struct cxl_port *port) cxl_endpoint_parse_cdat(port); cxl_port_map_bi(port); + cxl_bi_probe_capable(port); get_device(&cxlmd->dev); rc = devm_add_action_or_reset(&port->dev, schedule_detach, cxlmd); diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h index e507cb0f777f..80d942eb9456 100644 --- a/include/cxl/cxl.h +++ b/include/cxl/cxl.h @@ -169,6 +169,7 @@ struct cxl_dpa_partition { * @cxl_dvsec: Offset to the PCIe device DVSEC * @rcd: operating in RCD mode (CXL 3.0 9.11.8 CXL Devices Attached to an RCH) * @bi: device is BI (Back-Invalidate) enabled + * @bi_capable: device and topology path are BI capable * @media_ready: Indicate whether the device media is usable * @dpa_res: Overall DPA resource tree for the device * @part: DPA partition array @@ -189,6 +190,7 @@ struct cxl_dev_state { int cxl_dvsec; bool rcd; bool bi; + bool bi_capable; bool media_ready; struct resource dpa_res; struct cxl_dpa_partition part[CXL_NR_PARTITIONS_MAX]; -- 2.39.5