[PATCH 5/6] arm64: dts: allwinner: a523: add EPHY 25MHz clock fanout pins
Andre Przywara <[email protected]>
| Newsgroups | org.kernel.vger.linux-devicetree,dev.linux.lists.linux-sunxi,org.infradead.lists.linux-arm-kernel,org.kernel.vger.netdev |
|---|---|
| Message-ID | <[email protected]> |
The Allwinner A523 SoC family provides two clock fanout pins, which are backed by gated clocks fixed to 25 MHz, divided down from the main peripheral PLL. Those are meant to clock an Ethernet PHY, and allow to save an external crystal oscillator typically employed for that purpose. Add the pin descriptions of the two pins for those clocks, one is within the RGMII0 pins, the other within the RGMII1 pins, although the clock fanout works completely independently from the two MACs. Signed-off-by: Andre Przywara <[email protected]> --- arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi index ca6a16807049..1a95c0a21509 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -147,6 +147,20 @@ pio: pinctrl@2000000 { interrupt-controller; #interrupt-cells = <3>; + /omit-if-no-ref/ + ephy0_25m_pin: ephy0-25m-pin { + pins = "PH13"; + allwinner,pinmux = <5>; + function = "ephy_25m"; + }; + + /omit-if-no-ref/ + ephy1_25m_pin: ephy1-25m-pin { + pins = "PJ10"; + allwinner,pinmux = <5>; + function = "ephy_25m"; + }; + /omit-if-no-ref/ i2s2_pi_pins: i2s2-pi-pins { pins = "PI2", "PI3", "PI4", "PI5"; -- 2.43.0