Re: [PATCH v2 11/11] spi: dw: Add support for StarFive JHB100 SoC SFC

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The return value of `regmap_update_bits` is silently ignored in `dw_spi_jhb100_set_addr_nbyte`.
--

--- Patch [11]: [PATCH v2 11/11] spi: dw: Add support for StarFive JHB100 SoC SFC ---
commit 6fd643ebea16814890aa0dbec055ee773f4f746d
Author: Changhuang Liang <[email protected]>

spi: dw: Add support for StarFive JHB100 SoC SFC

This commit adds support for the StarFive JHB100 SoC SPI Flash Controller
(SFC). It introduces customizations to handle separate registers for
instruction and address, and utilizes a syscon to configure 3-byte/4-byte
address mode switching per chip select.

> diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c
> index 603e81a92c57a..8cdb0351605b2 100644
> --- a/drivers/spi/spi-dw-mmio.c
> +++ b/drivers/spi/spi-dw-mmio.c
[ ... ]
> @@ -310,6 +314,58 @@ static int dw_spi_elba_init(struct platform_device *pdev,
>  	return 0;
>  }
>  
> +static int dw_spi_jhb100_set_addr_nbyte(struct spi_device *spi, u8 nbyte)
> +{
> +	struct dw_spi *dws = spi_controller_get_devdata(spi->controller);
> +	struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws);
> +	struct regmap *syscon = dwsmmio->priv;
> +
> +	if (nbyte == 3) {
> +		regmap_update_bits(syscon, JHB100_ADDRMODE_CS,
> +				   BIT(spi_get_chipselect(spi, 0)),
> +				   0);
> +	} else if (nbyte == 4) {
> +		regmap_update_bits(syscon, JHB100_ADDRMODE_CS,
> +				   BIT(spi_get_chipselect(spi, 0)),
> +				   BIT(spi_get_chipselect(spi, 0)));

[Severity: Medium]
Is it intentional to silently ignore the return value of
regmap_update_bits() here?

If the regmap_update_bits() call fails, the hardware might be left in an
incorrect address mode (e.g., 3-byte instead of 4-byte). This could
silently corrupt subsequent SPI flash operations.

> +	} else {
> +		dev_err(&spi->dev, "Unsupported address nbyte %d\n", nbyte);
> +		return -EINVAL;
> +	}
> +
> +	return 0;
> +}

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=11