Re: [PATCH v2 09/11] spi: dw: detect enhanced spi mode

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Naive register read-back probing for OCTAL mode can incorrectly detect OCTAL support on QUAD-only hardware.
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--- Patch [9]: [PATCH v2 09/11] spi: dw: detect enhanced spi mode ---
commit 55207343ce55e6e564d0b04f2044bd3036ccb30f
Author: Sudip Mukherjee <[email protected]>

spi: dw: detect enhanced spi mode

This commit adds detection for enhanced SPI modes (dual, quad, octal) by
testing if the controller supports them via a register read-back. If
supported, it enables the DW_SPI_CAP_EMODE capability.

> diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c
> index cca8f4ba1004b..bfa017df7673f 100644
> --- a/drivers/spi/spi-dw-core.c
> +++ b/drivers/spi/spi-dw-core.c
[ ... ]
> @@ -1103,6 +1108,66 @@ static void dw_spi_cleanup(struct spi_device *spi)
>  	spi_set_ctldata(spi, NULL);
>  }
>  
> +static u16 detect_enh_mode(struct dw_spi *dws)
> +{
[ ... ]
> +	/* test octal mode */
> +	tmp_val = DW_SPI_CTRLR0_SPI_FRF_OCT_SPI << frf_shift;
> +	dw_writel(dws, DW_SPI_CTRLR0, tmp_val);
> +	if ((tmp_val & dw_readl(dws, DW_SPI_CTRLR0)) == tmp_val)
> +		mode |= SPI_TX_OCTAL | SPI_RX_OCTAL;

[Severity: High]
Could this read-back test incorrectly detect OCTAL support on hardware that
only supports up to QUAD mode?

Since DW_SPI_CTRLR0_SPI_FRF_OCT_SPI is 3, writing this to the 2-bit wide
SPI_FRF field will succeed if the hardware supports QUAD mode (value 2),
as the field is already 2 bits wide. The value will read back as 3 in the
register flip-flops even if the IP's internal state machine physically lacks
OCTAL support.

Can this falsely advertise SPI_TX_OCTAL and SPI_RX_OCTAL capabilities,
potentially leading to communication failure or hardware lockups when the
SPI flash driver attempts to use OCTAL mode?

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Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=9