Re: [PATCH v9 30/36] pinctrl: airoha: an7583: add support for olt pinmux

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Hardware Pin Multiplexing Conflict due to missing mutual exclusion in register masks between `olt` and `pon_alt`.
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--- Patch [30]: [PATCH v9 30/36] pinctrl: airoha: an7583: add support for olt pinmux ---
commit 83ceff2ddef41f5f471bb95f51c02740f7fc8a11
Author: Mikhail Kshevetskiy <[email protected]>

pinctrl: airoha: an7583: add support for olt pinmux

This commit adds support for the olt pin function for the olt pin group in
the airoha an7583 pinctrl driver.

> diff --git a/drivers/pinctrl/airoha/pinctrl-an7583.c b/drivers/pinctrl/airoha/pinctrl-an7583.c
> --- a/drivers/pinctrl/airoha/pinctrl-an7583.c
> +++ b/drivers/pinctrl/airoha/pinctrl-an7583.c
> @@ -393,6 +394,7 @@ static struct pinctrl_pin_desc pinctrl_pins[] = {
>  
>  static const int pon_pins[] = { 15, 16, 17, 18, 19, 20 };
>  static const int pon_alt_pins[] = { 36, 37, 38, 39, 40 };
> +static const int olt_pins[] = { 36, 37, 38, 39, 40 };

[ ... ]

> @@ -651,6 +655,19 @@ static const struct airoha_pinctrl_func_group pon_func_group[] = {
>  	},
>  };
>  
> +static const struct airoha_pinctrl_func_group olt_func_group[] = {
> +	{
> +		.name = "olt",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_PON_MODE,
> +			GPIO_OLT_MODE_MASK,
> +			GPIO_OLT_MODE_MASK
> +		},

[Severity: Medium]
Does this mask configuration safely handle mutually exclusive routing?

Since olt_pins and pon_alt_pins share the exact same physical pins,
should the bitmask for olt_func_group also include GPIO_PON_ALT_MODE_MASK
to ensure the pon_alt routing bit is cleared when olt is applied?

Similarly, pon_func_group does not appear to have been updated to clear
GPIO_OLT_MODE_MASK when pon_alt is activated. If a bootloader initially
configures pon_alt and the kernel later transitions the state to olt
(or vice versa during runtime pinmux state switches), could this leave
multiple routing bits set to 1 in REG_GPIO_PON_MODE and cause electrical
contention or incorrect IP block routing?

> +		.regmap_size = 1,
> +	},
> +};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=30