Re: [PATCH net-next v7 2/3] dt-bindings: dpll: add SiTime SiT95316 clock generator

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The DT binding example uses a VCO frequency that falls outside the hardware's documented valid bands.
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--- Patch [2]: [PATCH net-next v7 2/3] dt-bindings: dpll: add SiTime SiT95316 clock generator ---
commit 410e36c99d7032772301b076a8bb386cf2186fe9
Author: Ali Rouhi <[email protected]>

dt-bindings: dpll: add SiTime SiT95316 clock generator

This commit adds device tree binding documentation for the SiTime SiT95316
and SiT95317 DPLL clock generators.

> diff --git a/Documentation/devicetree/bindings/dpll/sitime,sit95316.yaml b/Documentation/devicetree/bindings/dpll/sitime,sit95316.yaml
> new file mode 100644
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dpll/sitime,sit95316.yaml
[ ... ]
> +  sitime,pll-fvco:
> +    $ref: /schemas/types.yaml#/definitions/uint64-array
> +    minItems: 4
> +    maxItems: 4
> +    description:
> +      Per-PLL VCO frequency in Hz for PLLA, PLLB, PLLC, PLLD.  Neither
> +      standard frequency suffix fits.  The VCO bands are 4915.2 MHz to
> +      5898.24 MHz and 6875 MHz to 7812.5 MHz, so every valid value
[ ... ]
> +examples:
> +  - |
> +    #include <dt-bindings/gpio/gpio.h>
> +    #include <dt-bindings/interrupt-controller/irq.h>
> +
> +    i2c {
> +        #address-cells = <1>;
> +        #size-cells = <0>;
> +
> +        dpll@68 {
> +            compatible = "sitime,sit95316";
> +            reg = <0x68>;
> +            clocks = <&xo2>;
> +            clock-names = "xtal";
> +            reset-gpios = <&gpio 78 GPIO_ACTIVE_LOW>;
> +            interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
> +            dpll-types = "eec", "eec", "eec", "eec";
> +            sitime,pll-fvco = /bits/ 64 <6251500000 0 0 0>;

[Severity: Low]
Does the example VCO frequency of 6251500000 (6251.5 MHz) fall into the
unsupported gap between the two valid operating bands?

The property description defines the valid bands as 4915.2 to 5898.24 MHz
and 6875 to 7812.5 MHz. Is there an additional supported frequency range
missing from the description, or should the example be updated to use a
value within the documented hardware limits?

> +            sitime,output-pll-map = <0 0 0 0 0 0 0 0 0 0 0 0>;
[ ... ]

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Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=2