Re: Re: [PATCH v5 08/12] gpio: pl061: add Ambarella CV75 register layout variant

On Wed, Aug 19, 2026 at 03:09:51PM +0800, zl020895 wrote:
> 
> I followed Linus' guidance on the v2 pinctrl patch to reuse gpio-pl061 with a
> per-variant register layout, because the Ambarella banks share the PL061
> interrupt register model (IS/IBE/IEV/IE/RIS/MIS/IC). gpio-mmio/gpio-regmap
> cover the DATA/DIR side well, but they seem not provide that IRQ controller,
> so moving there would need a separate irqchip and would risk duplicating the
> PL061 IRQ logic Linus asked us not to fork.
> 
> 
> Would you prefer we keep the PL061 variant for that reason, or is there a
> gpio-mmio/gpio-regmap approach that also covers this interrupt model cleanly?
> We can rework either way once that is clear.

I haven't told we should duplicate. My suggestion is:
- convert current gpio-pl061 to use gpio-mmio / gpio-regmap (and I vote for the latter)
- add new regmap configuration and necessary layout for your case.

> ---- Replied Message ----
> | From | Andy Shevchenko<[email protected]> |
> | Date | 08/18/2026 22:11 |
> On Tue, Aug 18, 2026 at 06:31:22PM +0800, Long Zhao via B4 Relay wrote:
> 
> > Extend gpio-pl061 with a per-variant register layout so the Ambarella
> > CV75 GPIO banks can reuse the PL061 driver instead of a duplicate.
> 
> This is reinvention of gpio-mmio.c (as a library). It has necessary facilities.
> Also gpio-regmap may be considered. So, switch this driver to use one of the
> above and the patch for the new device will be much simpler and elegant.

-- 
With Best Regards,
Andy Shevchenko