[PATCH v3 8/8] riscv: dts: eswin: add watchdog support
Pinkesh Vaghela <[email protected]> Tue, 4 Aug 2026 16:14:31 +0530
| Newsgroups | org.kernel.vger.linux-i2c,org.infradead.lists.linux-riscv,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-kernel |
|---|---|
| Message-ID | <[email protected]> |
From: Pritesh Patel <[email protected]> Add watchdog node for ESWIN EIC7700 SoC and enable them for HiFive Premier P550 board Signed-off-by: Pritesh Patel <[email protected]> Signed-off-by: Pinkesh Vaghela <[email protected]> --- .../dts/eswin/eic7700-hifive-premier-p550.dts | 16 ++++++++ arch/riscv/boot/dts/eswin/eic7700.dtsi | 40 +++++++++++++++++++ 2 files changed, 56 insertions(+) diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts index 50c15e08a57f..6f6cb45b3070 100644 --- a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts +++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts @@ -207,3 +207,19 @@ &uart2 { pinctrl-names = "default"; pinctrl-0 = <&uart2_pins>; }; + +&wdt0 { + status = "okay"; +}; + +&wdt1 { + status = "okay"; +}; + +&wdt2 { + status = "okay"; +}; + +&wdt3 { + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/eswin/eic7700.dtsi index c13432d14504..f873e9eeb929 100644 --- a/arch/riscv/boot/dts/eswin/eic7700.dtsi +++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi @@ -265,6 +265,46 @@ syscon: syscon@50440000 { }; }; + wdt0: watchdog@50800000 { + compatible = "snps,dw-wdt"; + reg = <0x0 0x50800000 0x0 0x4000>; + interrupts = <87>; + clocks = <&clk EIC7700_CLK_GATE_LSP_WDT0_PCLK>; + clock-names = "tclk"; + resets = <&reset EIC7700_RESET_WDT0>; + status = "disabled"; + }; + + wdt1: watchdog@50804000 { + compatible = "snps,dw-wdt"; + reg = <0x0 0x50804000 0x0 0x4000>; + interrupts = <88>; + clocks = <&clk EIC7700_CLK_GATE_LSP_WDT1_PCLK>; + clock-names = "tclk"; + resets = <&reset EIC7700_RESET_WDT1>; + status = "disabled"; + }; + + wdt2: watchdog@50808000 { + compatible = "snps,dw-wdt"; + reg = <0x0 0x50808000 0x0 0x4000>; + interrupts = <89>; + clocks = <&clk EIC7700_CLK_GATE_LSP_WDT2_PCLK>; + clock-names = "tclk"; + resets = <&reset EIC7700_RESET_WDT2>; + status = "disabled"; + }; + + wdt3: watchdog@5080c000 { + compatible = "snps,dw-wdt"; + reg = <0x0 0x5080c000 0x0 0x4000>; + interrupts = <90>; + clocks = <&clk EIC7700_CLK_GATE_LSP_WDT3_PCLK>; + clock-names = "tclk"; + resets = <&reset EIC7700_RESET_WDT3>; + status = "disabled"; + }; + uart0: serial@50900000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x50900000 0x0 0x10000>; -- 2.34.1