Re: [PATCH] PCI: j721e: Fix incorrect max_lanes for J7200

On 21/07/26 21:27, Takuma Fujiwara wrote:
> The PCIe Controller in the J7200 SoC supports a 4-lane configuration.
> However, j7200_pcie_rc_data and j7200_pcie_ep_data incorrectly set
> .max_lanes = 2, limiting operation to fewer lanes than the hardware
> supports.
> 
> Set .max_lanes = 4 for both j7200_pcie_rc_data and j7200_pcie_ep_data to
> match the hardware capability.
> 
> See J7200 Technical Reference Manual (SPRUIU1D), section 12.2.3.1.1
> for further details: https://www.ti.com/lit/pdf/spruiu1d

Thank you for identifying and fixing this.

> 
> Fixes: 3ac7f14084f5 ("PCI: j721e: Add per platform maximum lane settings")
> Signed-off-by: Takuma Fujiwara <[email protected]>

Reviewed-by: Siddharth Vadapalli <[email protected]>

> ---
>   drivers/pci/controller/cadence/pci-j721e.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
> index b29a35fbfb5f9..a029c4e9c05f6 100644
> --- a/drivers/pci/controller/cadence/pci-j721e.c
> +++ b/drivers/pci/controller/cadence/pci-j721e.c
> @@ -381,7 +381,7 @@ static const struct j721e_pcie_data j7200_pcie_rc_data = {
>   	.quirk_detect_quiet_flag = true,
>   	.linkdown_irq_regfield = J7200_LINK_DOWN,
>   	.byte_access_allowed = true,
> -	.max_lanes = 2,
> +	.max_lanes = 4,
>   };
>   
>   static const struct j721e_pcie_data j7200_pcie_ep_data = {
> @@ -389,7 +389,7 @@ static const struct j721e_pcie_data j7200_pcie_ep_data = {
>   	.quirk_detect_quiet_flag = true,
>   	.linkdown_irq_regfield = J7200_LINK_DOWN,
>   	.quirk_disable_flr = true,
> -	.max_lanes = 2,
> +	.max_lanes = 4,
>   };
>   
>   static const struct j721e_pcie_data am64_pcie_rc_data = {

Regards,
Siddharth.