Re: [PATCH v3 13/13] arm64: dts: qcom: Add SM7250 devicetree file
Abel Vesa <[email protected]>
| Newsgroups | org.kernel.vger.linux-pm,org.kernel.vger.linux-arm-msm,org.kernel.vger.linux-clk,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-kernel |
|---|---|
| Message-ID | <cgpmlh6hw3n67bgc7sxjrrixkxrxfsajnwwwucqzklef7zkusr@xiafwn2agcja> |
On 26-08-21 08:11:25, Sreeshankar K wrote: > Add base devicetree file for SM7250 SoC. > This file adds the basic nodes like cpu, psci and other required > configuration for booting up to the serial console. > > Signed-off-by: Sreeshankar K <[email protected]> > --- > arch/arm64/boot/dts/qcom/sm7250.dtsi | 612 +++++++++++++++++++++++++++ > 1 file changed, 612 insertions(+) > create mode 100644 arch/arm64/boot/dts/qcom/sm7250.dtsi > > diff --git a/arch/arm64/boot/dts/qcom/sm7250.dtsi b/arch/arm64/boot/dts/qcom/sm7250.dtsi > new file mode 100644 > index 000000000..7caa11c80 > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/sm7250.dtsi > @@ -0,0 +1,612 @@ > +// SPDX-License-Identifier: BSD-3-Clause > +/* > + * Copyright (c) 2026, Sreeshankar K <[email protected]> > + */ > + > +#include <dt-bindings/clock/qcom,rpmh.h> > +#include <dt-bindings/clock/qcom,sm7250-gcc.h> > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/power/qcom,rpmhpd.h> > +#include <dt-bindings/power/qcom-rpmpd.h> > +#include <dt-bindings/soc/qcom,rpmh-rsc.h> > + [...] > + > + cpu3: cpu@300 { > + device_type = "cpu"; > + compatible = "qcom,kryo475"; > + reg = <0x0 0x300>; > + clocks = <&cpufreq_hw 0>; > + enable-method = "psci"; > + next-level-cache = <&l2_300>; > + qcom,freq-domain = <&cpufreq_hw 0>; > + #cooling-cells = <2>; No capacity-dmips-mhz and dynamic-power-coefficient ? > + > + l2_300: l2-cache { > + compatible = "cache"; > + cache-level = <2>; > + cache-size = <0x20000>; > + cache-unified; > + next-level-cache = <&l3_0>; > + }; > + }; > + > + cpu4: cpu@400 { > + device_type = "cpu"; > + compatible = "qcom,kryo475"; > + reg = <0x0 0x400>; > + clocks = <&cpufreq_hw 0>; > + enable-method = "psci"; > + capacity-dmips-mhz = <1024>; > + dynamic-power-coefficient = <100>; > + next-level-cache = <&l2_400>; > + qcom,freq-domain = <&cpufreq_hw 0>; > + #cooling-cells = <2>; > + > + l2_400: l2-cache { > + compatible = "cache"; > + cache-level = <2>; > + cache-size = <0x20000>; > + cache-unified; > + next-level-cache = <&l3_0>; > + }; > + }; > + [...] > + > + apps_rsc: rsc@18200000 { > + compatible = "qcom,rpmh-rsc"; > + reg = <0x0 0x18200000 0x0 0x10000>, > + <0x0 0x18210000 0x0 0x10000>, > + <0x0 0x18220000 0x0 0x10000>; > + reg-names = "drv-0", "drv-1", "drv-2"; > + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; > + label = "apps_rsc"; > + qcom,tcs-offset = <0xd00>; > + qcom,drv-id = <2>; > + qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, > + <WAKE_TCS 3>, <CONTROL_TCS 1>; No power domain ?