[PATCH for-next 3/4] RDMA/bnxt_re: Add support for larger PBL pages for CQ
Selvin Xavier <[email protected]>
| Newsgroups | org.kernel.vger.linux-rdma |
|---|---|
| Message-ID | <[email protected]> |
Advertise the PBL page size and first-completion offset (FCO) in CREATE_CQ so the firmware can use huge-page CQ buffers. Signed-off-by: Saravanan Vajravel <[email protected]> Signed-off-by: Selvin Xavier <[email protected]> --- drivers/infiniband/hw/bnxt_re/ib_verbs.c | 9 +++++++++ drivers/infiniband/hw/bnxt_re/qplib_fp.c | 11 +++++++++-- drivers/infiniband/hw/bnxt_re/qplib_res.h | 1 + drivers/infiniband/hw/bnxt_re/roce_hsi.h | 13 ++++++++++++- 4 files changed, 31 insertions(+), 3 deletions(-) diff --git a/drivers/infiniband/hw/bnxt_re/ib_verbs.c b/drivers/infiniband/hw/bnxt_re/ib_verbs.c index 430d54f8f736..da4de44cf90d 100644 --- a/drivers/infiniband/hw/bnxt_re/ib_verbs.c +++ b/drivers/infiniband/hw/bnxt_re/ib_verbs.c @@ -3611,6 +3611,15 @@ int bnxt_re_create_user_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *att if (rc) goto free_umem; + /* + * The FCO field passed in the CREATE_CQ command is expressed in + * 32-byte units, so the offset must be a multiple of 32 bytes. + */ + if (cq->qplib_cq.sg_info.fwo_offset & (BIT(BNXT_QPLIB_CQ_FCO_SHIFT) - 1)) { + rc = -EINVAL; + goto free_umem; + } + cq->qplib_cq.dpi = &uctx->dpi; cq->qplib_cq.max_wqe = entries; cq->qplib_cq.coalescing = &rdev->cq_coalescing; diff --git a/drivers/infiniband/hw/bnxt_re/qplib_fp.c b/drivers/infiniband/hw/bnxt_re/qplib_fp.c index 5301e4f21ade..0319fe76c634 100644 --- a/drivers/infiniband/hw/bnxt_re/qplib_fp.c +++ b/drivers/infiniband/hw/bnxt_re/qplib_fp.c @@ -2147,9 +2147,16 @@ int bnxt_qplib_create_cq(struct bnxt_qplib_res *res, struct bnxt_qplib_cq *cq) pg_sz_lvl |= (cq->hwq.level & CMDQ_CREATE_CQ_LVL_MASK); req.pg_size_lvl = cpu_to_le32(pg_sz_lvl); req.pbl = cpu_to_le64(pbl->pg_map_arr[0]); + if (bnxt_re_pbl_size_supported(res->dattr->dev_cap_ext_flags_1)) { + req.flags |= cpu_to_le16(CMDQ_CREATE_CQ_FLAGS_PBL_PG_SIZE_VALID); + req.pbl_pg_size = bnxt_qplib_get_pbl_page_size(&cq->sg_info); + } req.cq_fco_cnq_id = cpu_to_le32( - (cq->cnq_hw_ring_id & CMDQ_CREATE_CQ_CNQ_ID_MASK) << - CMDQ_CREATE_CQ_CNQ_ID_SFT); + ((cq->cnq_hw_ring_id & CMDQ_CREATE_CQ_CNQ_ID_MASK) << + CMDQ_CREATE_CQ_CNQ_ID_SFT) | + (((cq->sg_info.fwo_offset >> BNXT_QPLIB_CQ_FCO_SHIFT) + << CMDQ_CREATE_CQ_CQ_FCO_SFT) & + CMDQ_CREATE_CQ_CQ_FCO_MASK)); bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), sizeof(resp), 0); rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); diff --git a/drivers/infiniband/hw/bnxt_re/qplib_res.h b/drivers/infiniband/hw/bnxt_re/qplib_res.h index ce6823af167e..d2b3835789f3 100644 --- a/drivers/infiniband/hw/bnxt_re/qplib_res.h +++ b/drivers/infiniband/hw/bnxt_re/qplib_res.h @@ -167,6 +167,7 @@ struct bnxt_qplib_sg_info { u32 pgshft; u32 pgsize; #define BNXT_QPLIB_QP_FWO_SHIFT 12 /* FWO is conveyed to firmware in 4K units */ +#define BNXT_QPLIB_CQ_FCO_SHIFT 5 /* FCO is conveyed to firmware in 32-byte units */ u32 fwo_offset; /* first-word offset into huge page */ bool nopte; }; diff --git a/drivers/infiniband/hw/bnxt_re/roce_hsi.h b/drivers/infiniband/hw/bnxt_re/roce_hsi.h index c89fc54f61c3..bbcd723cd2b5 100644 --- a/drivers/infiniband/hw/bnxt_re/roce_hsi.h +++ b/drivers/infiniband/hw/bnxt_re/roce_hsi.h @@ -1146,6 +1146,7 @@ struct cmdq_create_cq { #define CMDQ_CREATE_CQ_FLAGS_STEERING_TAG_VALID 0x2UL #define CMDQ_CREATE_CQ_FLAGS_INFINITE_CQ_MODE 0x4UL #define CMDQ_CREATE_CQ_FLAGS_COALESCING_VALID 0x8UL + #define CMDQ_CREATE_CQ_FLAGS_PBL_PG_SIZE_VALID 0x10UL __le16 cookie; u8 resp_size; u8 reserved8; @@ -1178,7 +1179,17 @@ struct cmdq_create_cq { __le32 cq_size; __le64 pbl; __le16 steering_tag; - u8 reserved48[2]; + u8 pbl_pg_size; + #define CMDQ_CREATE_CQ_PBL_PG_SIZE_MASK 0x7UL + #define CMDQ_CREATE_CQ_PBL_PG_SIZE_SFT 0 + #define CMDQ_CREATE_CQ_PBL_PG_SIZE_PG_4K 0x0UL + #define CMDQ_CREATE_CQ_PBL_PG_SIZE_PG_8K 0x1UL + #define CMDQ_CREATE_CQ_PBL_PG_SIZE_PG_64K 0x2UL + #define CMDQ_CREATE_CQ_PBL_PG_SIZE_PG_2M 0x3UL + #define CMDQ_CREATE_CQ_PBL_PG_SIZE_PG_8M 0x4UL + #define CMDQ_CREATE_CQ_PBL_PG_SIZE_PG_1G 0x5UL + #define CMDQ_CREATE_CQ_PBL_PG_SIZE_LAST CMDQ_CREATE_CQ_PBL_PG_SIZE_PG_1G + u8 reserved8_1; __le32 coalescing; #define CMDQ_CREATE_CQ_BUF_MAXTIME_MASK 0x1ffUL #define CMDQ_CREATE_CQ_BUF_MAXTIME_SFT 0 -- 2.39.3