[PATCH v2 3/9] clk: renesas: rzg2l: Rename cpg_core_clk::flag to core_flags
Biju <[email protected]>
| Newsgroups | org.kernel.vger.linux-renesas-soc,org.kernel.vger.linux-clk,org.kernel.vger.linux-kernel |
|---|---|
| Message-ID | <[email protected]> |
From: Biju Das <[email protected]> Rename the 'flag' member of struct cpg_core_clk to 'core_flags' for clarity and to better distinguish it from mux_flags. Update all users and DEF_* macros accordingly. No functional change. Signed-off-by: Biju Das <[email protected]> --- v2: * New patch. --- drivers/clk/renesas/rzg2l-cpg.c | 10 +++++----- drivers/clk/renesas/rzg2l-cpg.h | 20 ++++++++++---------- 2 files changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index 9730ef67fbc6..07b78cbc4531 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -433,7 +433,7 @@ rzg3s_cpg_div_clk_register(const struct cpg_core_clk *core, struct rzg2l_cpg_pri return ERR_PTR(-ENOMEM); init.name = core->name; - init.flags = core->flag; + init.flags = core->core_flags; init.ops = &rzg3s_div_clk_ops; init.parent_names = &parent_name; init.num_parents = 1; @@ -491,7 +491,7 @@ rzg2l_cpg_div_clk_register(const struct cpg_core_clk *core, base + GET_REG_OFFSET(core->conf), GET_SHIFT(core->conf), GET_WIDTH(core->conf), - core->flag, + core->core_flags, core->dtable, &priv->rmw_lock); else @@ -500,7 +500,7 @@ rzg2l_cpg_div_clk_register(const struct cpg_core_clk *core, base + GET_REG_OFFSET(core->conf), GET_SHIFT(core->conf), GET_WIDTH(core->conf), - core->flag, &priv->rmw_lock); + core->core_flags, &priv->rmw_lock); if (IS_ERR(clk_hw)) return ERR_CAST(clk_hw); @@ -516,7 +516,7 @@ rzg2l_cpg_mux_clk_register(const struct cpg_core_clk *core, clk_hw = devm_clk_hw_register_mux(priv->dev, core->name, core->parent_names, core->num_parents, - core->flag, + core->core_flags, priv->base + GET_REG_OFFSET(core->conf), GET_SHIFT(core->conf), GET_WIDTH(core->conf), @@ -595,7 +595,7 @@ rzg2l_cpg_sd_mux_clk_register(const struct cpg_core_clk *core, init.name = core->name; init.ops = &rzg2l_cpg_sd_clk_mux_ops; - init.flags = core->flag; + init.flags = core->core_flags; init.num_parents = core->num_parents; init.parent_names = core->parent_names; diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h index 41e8f389c566..38db209aabf9 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -110,7 +110,7 @@ struct cpg_core_clk { }; const char * const *parent_names; notifier_fn_t notifier; - u32 flag; + u32 core_flags; u32 mux_flags; int num_parents; }; @@ -168,24 +168,24 @@ enum clk_types { #define DEF_DIV(_name, _id, _parent, _conf, _dtable) \ DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \ .parent = _parent, .dtable = _dtable, \ - .flag = CLK_DIVIDER_HIWORD_MASK) + .core_flags = CLK_DIVIDER_HIWORD_MASK) #define DEF_DIV_RO(_name, _id, _parent, _conf, _dtable) \ DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \ .parent = _parent, .dtable = _dtable, \ - .flag = CLK_DIVIDER_READ_ONLY) + .core_flags = CLK_DIVIDER_READ_ONLY) #define DEF_G3S_DIV(_name, _id, _parent, _conf, _sconf, _dtable, _invalid_rate, \ _max_rate, _clk_flags, _notif) \ DEF_TYPE(_name, _id, CLK_TYPE_G3S_DIV, .conf = _conf, .sconf = _sconf, \ .parent = _parent, .dtable = _dtable, \ .invalid_rate = _invalid_rate, \ - .max_rate = _max_rate, .flag = (_clk_flags), \ + .max_rate = _max_rate, .core_flags = (_clk_flags), \ .notifier = _notif) -#define DEF_MUX_FLAGS(_name, _id, _conf, _parent_names, _flag) \ +#define DEF_MUX_FLAGS(_name, _id, _conf, _parent_names, _flags) \ DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \ .parent_names = _parent_names, \ .num_parents = ARRAY_SIZE(_parent_names), \ .mux_flags = CLK_MUX_HIWORD_MASK, \ - .flag = _flag) + .core_flags = _flags) #define DEF_MUX(_name, _id, _conf, _parent_names) \ DEF_MUX_FLAGS(_name, _id, _conf, _parent_names, 0) #define DEF_MUX_RO(_name, _id, _conf, _parent_names) \ @@ -197,18 +197,18 @@ enum clk_types { DEF_TYPE(_name, _id, CLK_TYPE_SD_MUX, .conf = _conf, .sconf = _sconf, \ .parent_names = _parent_names, \ .num_parents = ARRAY_SIZE(_parent_names), \ - .mtable = _mtable, .flag = _clk_flags, .notifier = _notifier) + .mtable = _mtable, .core_flags = _clk_flags, .notifier = _notifier) #define DEF_PLL5_FOUTPOSTDIV(_name, _id, _parent) \ DEF_TYPE(_name, _id, CLK_TYPE_SIPLL5, .parent = _parent) #define DEF_PLL5_4_MUX(_name, _id, _conf, _parent_names) \ DEF_TYPE(_name, _id, CLK_TYPE_PLL5_4_MUX, .conf = _conf, \ .parent_names = _parent_names, \ .num_parents = ARRAY_SIZE(_parent_names)) -#define DEF_DSI_DIV(_name, _id, _parent, _flag) \ - DEF_TYPE(_name, _id, CLK_TYPE_DSI_DIV, .parent = _parent, .flag = _flag) +#define DEF_DSI_DIV(_name, _id, _parent, _flags) \ + DEF_TYPE(_name, _id, CLK_TYPE_DSI_DIV, .parent = _parent, .core_flags = _flags) #define DEF_G3L_DSI_DIV(_name, _id, _parent, _conf) \ DEF_TYPE(_name, _id, CLK_TYPE_G3L_DSI_DIV, .parent = _parent, .conf = _conf, \ - .flag = CLK_SET_RATE_PARENT) + .core_flags = CLK_SET_RATE_PARENT) #define DEF_G3L_PLLDSI(_name, _id, _parent, _conf) \ DEF_TYPE(_name, _id, CLK_TYPE_G3L_PLLDSI, .parent = _parent, .conf = _conf) -- 2.43.0