[PATCH RFC v2 9/9] arm64: dts: renesas: r9a09g087: Use SYS syscon for WDTDCR access
Prabhakar <[email protected]>
| Newsgroups | org.kernel.vger.linux-watchdog,org.kernel.vger.linux-clk,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-kernel,org.kernel.vger.linux-renesas-soc |
|---|---|
| Message-ID | <[email protected]> |
From: Lad Prabhakar <[email protected]> The WDTDCR registers for wdt0-wdt5 reside in the second region of the System Controller (SYSC) block at 0x81290000, which is now managed by the dedicated SYSC driver and exposed via a unified syscon regmap interface. Replace the direct mapping of the individual WDTDCR registers with the new "renesas,sys" phandle property pointing to the SYS syscon node. Signed-off-by: Lad Prabhakar <[email protected]> --- v1->v2: - No change. --- arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 24 +++++++++++----------- 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi index 165c404dfd36..90a2fd02ae89 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi @@ -327,61 +327,61 @@ channel1 { wdt0: watchdog@80082000 { compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt"; - reg = <0 0x80082000 0 0x400>, - <0 0x81295100 0 0x04>; + reg = <0 0x80082000 0 0x400>; clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>; clock-names = "pclk"; power-domains = <&cpg>; + renesas,sys = <&sys1 0>; status = "disabled"; }; wdt1: watchdog@80082400 { compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt"; - reg = <0 0x80082400 0 0x400>, - <0 0x81295104 0 0x04>; + reg = <0 0x80082400 0 0x400>; clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>; clock-names = "pclk"; power-domains = <&cpg>; + renesas,sys = <&sys1 1>; status = "disabled"; }; wdt2: watchdog@80082800 { compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt"; - reg = <0 0x80082800 0 0x400>, - <0 0x81295108 0 0x04>; + reg = <0 0x80082800 0 0x400>; clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>; clock-names = "pclk"; power-domains = <&cpg>; + renesas,sys = <&sys1 2>; status = "disabled"; }; wdt3: watchdog@80082c00 { compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt"; - reg = <0 0x80082c00 0 0x400>, - <0 0x8129510c 0 0x04>; + reg = <0 0x80082c00 0 0x400>; clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>; clock-names = "pclk"; power-domains = <&cpg>; + renesas,sys = <&sys1 3>; status = "disabled"; }; wdt4: watchdog@80083000 { compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt"; - reg = <0 0x80083000 0 0x400>, - <0 0x81295110 0 0x04>; + reg = <0 0x80083000 0 0x400>; clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>; clock-names = "pclk"; power-domains = <&cpg>; + renesas,sys = <&sys1 4>; status = "disabled"; }; wdt5: watchdog@80083400 { compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt"; - reg = <0 0x80083400 0 0x400>, - <0 0x81295114 0 0x04>; + reg = <0 0x80083400 0 0x400>; clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>; clock-names = "pclk"; power-domains = <&cpg>; + renesas,sys = <&sys1 5>; status = "disabled"; }; -- 2.54.0