Re: [PATCH v2 2/3] phy: qcom: qmp-pcie: Add pcs_lane1 offset to V5 offsets
Dmitry Baryshkov <[email protected]> Wed, 22 Jul 2026 01:51:50 +0300
| Newsgroups | org.kernel.vger.phone-devel,org.infradead.lists.linux-phy,org.kernel.vger.linux-arm-msm,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-kernel |
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| Message-ID | <vnqbthpnjfgwm3bsp3lysfhugxfljd3cictjmwvn4kuavytvmt@lwkhsuydhamk> |
On Wed, Jul 15, 2026 at 02:37:47AM -0400, Esteban Urrutia wrote: > Some SoCs such as SM8475 write data to registers using this offset, > specifically SW_CTRL2 and MX_CTRL2. > Add pcs_lane1 offset to V5 offsets to support this. > > Signed-off-by: Esteban Urrutia <[email protected]> > --- > drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 1 + > 1 file changed, 1 insertion(+) > Fixes: 0fd0b31965b0 ("phy: qualcomm: qmp-pcie: add support for SAR2130P") Reviewed-by: Dmitry Baryshkov <[email protected]> -- With best wishes Dmitry