Re: [PATCH v2 2/2] arm64: dts: qcom: milos: add CPU OPP table with DDR & L3 bandwidths

On Fri, Jul 17, 2026 at 03:33:04PM +0200, Luca Weiss wrote:
> Add the OSC L3 Cache controller node, interconnect entry for each CPU,
> with 2 different paths (CPU to DDR, L3 Cache from CPU to DDR interface),
> and add the OPP tables for each CPU clusters (cpu0-3, cpu4-6 & cpu7) to
> permit scaling the DDR and L3 cache frequency by aggregating bandwidth
> requests of all CPU core with reference to the current OPP they are
> configured in by the LMH/EPSS hardware.
> 
> The effect is a proper caches & DDR frequency scaling when CPU cores
> change frequency.
> 
> The OPP tables were built using the downstream memlat ddr & l3 tables
> for each cluster type with the actual EPSS cpufreq LUT tables from
> running devices. Note, that higher frequencies than SM7635 are available
> on QCS6690, those have been added here as far as possible but may not be
> fully complete. Additional OPPs may need to be added for that SoC.
> 
> Reviewed-by: Konrad Dybcio <[email protected]>
> Signed-off-by: Luca Weiss <[email protected]>
> ---
>  arch/arm64/boot/dts/qcom/milos.dtsi | 344 ++++++++++++++++++++++++++++++++++++
>  1 file changed, 344 insertions(+)
> 

Reviewed-by: Dmitry Baryshkov <[email protected]>


-- 
With best wishes
Dmitry