Exchanging data between CPU and FPGA through shared DDR

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Hi,
I'm working on a SoC where both the CPU and an FPGA have access to the same
DDR memory. I need to exchange data between them.
One idea I have is to reserve a portion of DDR via the device tree
(reserved-memory node), so that the kernel will not use it, and then use
ioremap (or similar) to expose that region to user space so an application
can communicate with the FPGA.
Is this the right approach, or is there a more recommended mechanism in the
kernel for CPU - FPGA data exchange using shared DDR?

Best regards
Patryk

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<div dir=3D"ltr">Hi,<br>I&#39;m working on a SoC where both the CPU and an =
FPGA have access to the same DDR memory. I need to exchange data between th=
em.<br>One idea I have is to reserve a portion of DDR via the device tree (=
reserved-memory node), so that the kernel will not use it, and then use ior=
emap (or similar) to expose that region to user space so an application can=
 communicate with the FPGA. <br><div>Is this the right approach, or is ther=
e a more recommended mechanism in the kernel for CPU - FPGA data exchange u=
sing shared DDR?</div><div><br></div><div>Best regards</div><div>Patryk</di=
v><br></div>

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