[PATCH 06/20] target/arm: Implement SVE BFSCALE
Richard Henderson <[email protected]>
| Newsgroups | org.nongnu.qemu-arm,org.nongnu.qemu-devel |
|---|---|
| Message-ID | <[email protected]> |
Signed-off-by: Richard Henderson <[email protected]> --- target/arm/cpu-features.h | 5 +++++ target/arm/tcg/helper-sve-defs.h | 2 ++ target/arm/tcg/sve_helper.c | 1 + target/arm/tcg/translate-sve.c | 2 ++ target/arm/tcg/sve.decode | 5 ++++- 5 files changed, 14 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index e444397a47..76859c1f74 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -1580,6 +1580,11 @@ static inline bool isar_feature_aa64_sve_b16b16(const ARMISARegisters *id) return FIELD_EX64_IDREG(id, ID_AA64ZFR0, B16B16); } +static inline bool isar_feature_aa64_sve_bfscale(const ARMISARegisters *id) +{ + return FIELD_EX64_IDREG(id, ID_AA64ZFR0, B16B16) >= 2; +} + static inline bool isar_feature_aa64_ssve_fexpa(const ARMISARegisters *id) { return FIELD_EX64_IDREG(id, ID_AA64SMFR0, SFEXPA); diff --git a/target/arm/tcg/helper-sve-defs.h b/target/arm/tcg/helper-sve-defs.h index 19bd936f6e..f78e77662d 100644 --- a/target/arm/tcg/helper-sve-defs.h +++ b/target/arm/tcg/helper-sve-defs.h @@ -1303,6 +1303,8 @@ DEF_HELPER_FLAGS_6(sve_ah_fabd_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_ah_fabd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_6(sve_fscalbn_b16, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, fpst, i32) DEF_HELPER_FLAGS_6(sve_fscalbn_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, fpst, i32) DEF_HELPER_FLAGS_6(sve_fscalbn_s, TCG_CALL_NO_RWG, diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index ac96b18784..8389dce629 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -4827,6 +4827,7 @@ DO_ZPZZ_FP(sve_ah_fabd_h, uint16_t, H1_2, ah_abd_h) DO_ZPZZ_FP(sve_ah_fabd_s, uint32_t, H1_4, ah_abd_s) DO_ZPZZ_FP(sve_ah_fabd_d, uint64_t, H1_8, ah_abd_d) +DO_ZPZZ_FP(sve_fscalbn_b16, int16_t, H1_2, bfloat16_scalbn) DO_ZPZZ_FP(sve_fscalbn_h, int16_t, H1_2, float16_scalbn) DO_ZPZZ_FP(sve_fscalbn_s, int32_t, H1_4, float32_scalbn) DO_ZPZZ_FP(sve_fscalbn_d, int64_t, H1_8, scalbn_d) diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 919ff1b217..52f370e47e 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -4505,6 +4505,8 @@ static gen_helper_gvec_4_ptr * const sve_fscalbn_zpzz_fns[4] = { }; TRANS_FEAT(FSCALE, aa64_sme_or_sve, gen_gvec_fpst_arg_zpzz, sve_fscalbn_zpzz_fns[a->esz], a) +TRANS_FEAT(BFSCALE, aa64_sve_bfscale, gen_gvec_fpst_arg_zpzz, + gen_helper_sve_fscalbn_b16, a) static gen_helper_gvec_4_ptr * const sve_fdiv_zpzz_fns[4] = { NULL, diff --git a/target/arm/tcg/sve.decode b/target/arm/tcg/sve.decode index 07dac681ac..ed19ae237f 100644 --- a/target/arm/tcg/sve.decode +++ b/target/arm/tcg/sve.decode @@ -1196,7 +1196,10 @@ FSUB_zpzz 01100101 .. 00 0011 100 ... ..... ..... @rdm_pg_rn # FSUBR FMIN_zpzz 01100101 .. 00 0111 100 ... ..... ..... @rdn_pg_rm } FABD 01100101 .. 00 1000 100 ... ..... ..... @rdn_pg_rm -FSCALE 01100101 .. 00 1001 100 ... ..... ..... @rdn_pg_rm +{ + BFSCALE 01100101 00 00 1001 100 ... ..... ..... @rdn_pg_rm_e0 + FSCALE 01100101 .. 00 1001 100 ... ..... ..... @rdn_pg_rm +} FMULX 01100101 .. 00 1010 100 ... ..... ..... @rdn_pg_rm FDIV 01100101 .. 00 1100 100 ... ..... ..... @rdm_pg_rn # FDIVR FDIV 01100101 .. 00 1101 100 ... ..... ..... @rdn_pg_rm -- 2.43.0