[PATCH 07/20] target/arm: Implement SME BFSCALE
Richard Henderson <[email protected]>
| Newsgroups | org.nongnu.qemu-arm,org.nongnu.qemu-devel |
|---|---|
| Message-ID | <[email protected]> |
Signed-off-by: Richard Henderson <[email protected]> --- target/arm/cpu-features.h | 5 +++++ target/arm/tcg/helper-a64-defs.h | 1 + target/arm/tcg/translate-sme.c | 4 ++++ target/arm/tcg/vec_helper64.c | 1 + target/arm/tcg/sme.decode | 20 ++++++++++++++++---- 5 files changed, 27 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 76859c1f74..b29cd49020 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -1872,6 +1872,11 @@ static inline bool isar_feature_aa64_sme_tmop_f8f32(const ARMISARegisters *id) return isar_feature_aa64_sme_tmop(id) && isar_feature_aa64_sme_f8f32(id); } +static inline bool isar_feature_aa64_sme2_sve_bfscale(const ARMISARegisters *id) +{ + return isar_feature_aa64_sme2(id) && isar_feature_aa64_sve_bfscale(id); +} + /* * Feature tests for "does this exist in either 32-bit or 64-bit?" */ diff --git a/target/arm/tcg/helper-a64-defs.h b/target/arm/tcg/helper-a64-defs.h index 0e56e00f45..582d160850 100644 --- a/target/arm/tcg/helper-a64-defs.h +++ b/target/arm/tcg/helper-a64-defs.h @@ -152,6 +152,7 @@ DEF_HELPER_FLAGS_5(gvec_famin_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32 DEF_HELPER_FLAGS_5(gvec_famax_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) DEF_HELPER_FLAGS_5(gvec_famin_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fscale_b16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) DEF_HELPER_FLAGS_5(gvec_fscale_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) DEF_HELPER_FLAGS_5(gvec_fscale_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) DEF_HELPER_FLAGS_5(gvec_fscale_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index 463754b057..d28574a8cf 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -890,6 +890,10 @@ static gen_helper_gvec_3_ptr * const f_vector_fscale[4] = { }; TRANS_FEAT(FSCALE_n1, aa64_sme2_f8cvt, do_zzz_n1_fpst, a, f_vector_fscale[a->esz]) TRANS_FEAT(FSCALE_nn, aa64_sme2_f8cvt, do_zzz_nn_fpst, a, f_vector_fscale[a->esz]) +TRANS_FEAT(BFSCALE_n1, aa64_sme2_sve_bfscale, do_zzz_n1_fpst, a, + gen_helper_gvec_fscale_b16) +TRANS_FEAT(BFSCALE_nn, aa64_sme2_sve_bfscale, do_zzz_nn_fpst, a, + gen_helper_gvec_fscale_b16) static gen_helper_gvec_3_ptr * const f_vector_fmul[4] = { NULL, diff --git a/target/arm/tcg/vec_helper64.c b/target/arm/tcg/vec_helper64.c index d8b25b868e..8879969350 100644 --- a/target/arm/tcg/vec_helper64.c +++ b/target/arm/tcg/vec_helper64.c @@ -179,6 +179,7 @@ DO_3OP(gvec_famin_s, float32_famin, float32) DO_3OP(gvec_famax_d, float64_famax, float64) DO_3OP(gvec_famin_d, float64_famin, float64) +DO_3OP(gvec_fscale_b16, bfloat16_scalbn, int16_t) DO_3OP(gvec_fscale_h, float16_scalbn, int16_t) DO_3OP(gvec_fscale_s, float32_scalbn, int32_t) DO_3OP(gvec_fscale_d, scalbn_d, int64_t) diff --git a/target/arm/tcg/sme.decode b/target/arm/tcg/sme.decode index 60c7cacc10..4e19c42b19 100644 --- a/target/arm/tcg/sme.decode +++ b/target/arm/tcg/sme.decode @@ -287,8 +287,14 @@ ADD_n1 1100000 1 .. 10 .... 1010.0 11000 .... 0 @z2z_4x1 SQDMULH_n1 1100000 1 .. 10 .... 1010.1 00000 .... 0 @z2z_2x1 SQDMULH_n1 1100000 1 .. 10 .... 1010.1 00000 .... 0 @z2z_4x1 -FSCALE_n1 1100000 1 .. 10 .... 1010.0 01100 .... 0 @z2z_2x1 -FSCALE_n1 1100000 1 .. 10 .... 1010.0 01100 .... 0 @z2z_4x1 +{ + BFSCALE_n1 1100000 1 00 10 .... 1010.0 01100 .... 0 @z2z_2x1_e0 + FSCALE_n1 1100000 1 .. 10 .... 1010.0 01100 .... 0 @z2z_2x1 +} +{ + BFSCALE_n1 1100000 1 00 10 .... 1010.0 01100 .... 0 @z2z_4x1_e0 + FSCALE_n1 1100000 1 .. 10 .... 1010.0 01100 .... 0 @z2z_4x1 +} FMUL_n1 1100000 1 esz:2 1 zm:4 0 111010 ....0 ....0 \ &zzz_en n=2 zd=%zd_ax2 zn=%zn_ax2 @@ -365,8 +371,14 @@ FAMAX_nn 1100000 1 .. 1 ..... 1011.0 01010 .... 0 @z2z_4x4 FAMIN_nn 1100000 1 .. 1 ..... 1011.0 01010 .... 1 @z2z_2x2 FAMIN_nn 1100000 1 .. 1 ..... 1011.0 01010 .... 1 @z2z_4x4 -FSCALE_nn 1100000 1 .. 1 ..... 1011.0 01100 .... 0 @z2z_2x2 -FSCALE_nn 1100000 1 .. 1 ..... 1011.0 01100 .... 0 @z2z_4x4 +{ + BFSCALE_nn 1100000 1 00 1 ..... 1011.0 01100 .... 0 @z2z_2x2_e0 + FSCALE_nn 1100000 1 .. 1 ..... 1011.0 01100 .... 0 @z2z_2x2 +} +{ + BFSCALE_nn 1100000 1 00 1 ..... 1011.0 01100 .... 0 @z2z_4x4_e0 + FSCALE_nn 1100000 1 .. 1 ..... 1011.0 01100 .... 0 @z2z_4x4 +} FMUL_nn 1100000 1 esz:2 1 ....0 111001 ....0 ....0 \ &zzz_en n=2 zd=%zd_ax2 zn=%zn_ax2 zm=%zm_ax2 -- 2.43.0