Re: [PATCH v2 09/10] target/arm: Annotate arch revisions in aarch64_max_tcg_initfn
Peter Maydell <[email protected]>
| Newsgroups | org.nongnu.qemu-arm,org.nongnu.qemu-devel |
|---|---|
| Message-ID | <CAFEAcA-bLDVEqqJs+Ty+s8nKbfDOzAxwXW4f6z7iPNcAKHgKqA@mail.gmail.com> |
On Wed, 12 Aug 2026 at 21:46, Richard Henderson <[email protected]> wrote: > > Annotate the minimum revion from which each feature is OPTIONAL. > Modulo some sorting of properties at the end, comment changes only. > > Signed-off-by: Richard Henderson <[email protected]> > + t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.1: FEAT_FlagM2 */ FEAT_FlagM2 is optional from v8.4 > t = GET_IDREG(isar, ID_AA64ISAR2); > - t = FIELD_DP64(t, ID_AA64ISAR2, RPRES, 1); /* FEAT_RPRES */ > - t = FIELD_DP64(t, ID_AA64ISAR2, MOPS, 1); /* FEAT_MOPS */ > - t = FIELD_DP64(t, ID_AA64ISAR2, BC, 1); /* FEAT_HBC */ > - t = FIELD_DP64(t, ID_AA64ISAR2, WFXT, 2); /* FEAT_WFxT */ > - t = FIELD_DP64(t, ID_AA64ISAR2, CSSC, 2); /* FEAT_CSSC, FEAT_CMPBR */ > - t = FIELD_DP64(t, ID_AA64ISAR2, LUT, 1); /* FEAT_LUT */ > - t = FIELD_DP64(t, ID_AA64ISAR2, ATS1A, 1); /* FEAT_ATS1A */ > + t = FIELD_DP64(t, ID_AA64ISAR2, RPRES, 1); /* v8.6: FEAT_RPRES */ > + t = FIELD_DP64(t, ID_AA64ISAR2, MOPS, 1); /* v8.7: FEAT_MOPS */ > + t = FIELD_DP64(t, ID_AA64ISAR2, BC, 1); /* v8.7: FEAT_HBC */ > + t = FIELD_DP64(t, ID_AA64ISAR2, WFXT, 2); /* v8.6: FEAT_WFxT */ existing thing, but WFXT is in [3:0], so out of order here > + t = FIELD_DP64(t, ID_AA64ISAR2, CSSC, 2); /* v9.3: FEAT_CMPBR */ > + t = FIELD_DP64(t, ID_AA64ISAR2, LUT, 1); /* v9.2: FEAT_LUT */ > + t = FIELD_DP64(t, ID_AA64ISAR2, ATS1A, 1); /* v8.8: FEAT_ATS1A */ > SET_IDREG(isar, ID_AA64ISAR2, t); > t = GET_IDREG(isar, ID_AA64MMFR0); > - t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */ > - t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 1); /* 16k pages supported */ > - t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* 16k stage2 supported */ > - t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 supported */ > - t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 supported */ > - t = FIELD_DP64(t, ID_AA64MMFR0, FGT, 1); /* FEAT_FGT */ > - t = FIELD_DP64(t, ID_AA64MMFR0, ECV, 2); /* FEAT_ECV */ > + t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* v8.1: FEAT_LPA: 52 bits */ > + t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 1); /* v8.0: FEAT_TGran16K */ > + t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* v8.0: FEAT_S2TGran4K */ 16K, not 4 > + t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* v8.0: FEAT_S2TGran64K */ > + t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* v8.0: FEAT_S2TGran4K */ > + t = FIELD_DP64(t, ID_AA64MMFR0, FGT, 1); /* v8.5: FEAT_FGT */ > + t = FIELD_DP64(t, ID_AA64MMFR0, ECV, 2); /* v8.5: FEAT_ECV */ Existing thing: 2 is FEAT_ECV_POFF (optional from v8.5). FEAT_ECV is ECV==1. > t = GET_IDREG(isar, ID_AA64MMFR3); > - t = FIELD_DP64(t, ID_AA64MMFR3, TCRX, 1); /* FEAT_TCR2 */ > - t = FIELD_DP64(t, ID_AA64MMFR3, SCTLRX, 1); /* FEAT_SCTLR2 */ > - t = FIELD_DP64(t, ID_AA64MMFR3, MEC, 1); /* FEAT_MEC */ > - t = FIELD_DP64(t, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPEC */ > - t = FIELD_DP64(t, ID_AA64MMFR3, S1PIE, 1); /* FEAT_S1PIE */ > - t = FIELD_DP64(t, ID_AA64MMFR3, S2PIE, 1); /* FEAT_S2PIE */ > - t = FIELD_DP64(t, ID_AA64MMFR3, AIE, 1); /* FEAT_AIE */ > + t = FIELD_DP64(t, ID_AA64MMFR3, TCRX, 1); /* v8.0: FEAT_TCR2 */ > + t = FIELD_DP64(t, ID_AA64MMFR3, SCTLRX, 1); /* v8.0: FEAT_SCTLR2 */ > + t = FIELD_DP64(t, ID_AA64MMFR3, MEC, 1); /* v9.2: FEAT_MEC */ > + t = FIELD_DP64(t, ID_AA64MMFR3, SPEC_FPACC, 1); /* v8.2: FEAT_FPACC_SPEC */ Existing thing: MEC and SPEC_FPACC are out of order here and should be after AIE. > + t = FIELD_DP64(t, ID_AA64MMFR3, S1PIE, 1); /* v8.8: FEAT_S1PIE */ > + t = FIELD_DP64(t, ID_AA64MMFR3, S2PIE, 1); /* v8.8: FEAT_S2PIE */ > + t = FIELD_DP64(t, ID_AA64MMFR3, AIE, 1); /* v8.8: FEAT_AIE */ > SET_IDREG(isar, ID_AA64MMFR3, t); Otherwise Reviewed-by: Peter Maydell <[email protected]> -- PMM