[PATCH v2 0/3] Correct cbo and lq disassembly

From: Frédéric Pétrot <[email protected]>

The CBO instructions were, AFAIU, disassembled erroneously.
In addition, lq (load-quad, a RV128 instruction) shares the same
opcode space as the CBOs, which also led to incorrect dasm for that
instruction (understandable since RV128 is an experimental feature).
To avoid overlaps, we now require that lq is decoded only if
rd is not 0, as CBO requires the field corresponding to rd to be zero,
both in dasm and decodetree.

Change in v2: 
- Move the last v1 patch to the first place to correct the original
  indentation that was making checkpatch unhappy before doing the
  real work.
  (Note that disas/riscv.c has overall many checkpatch issues, this
  patch only solves the indentation one, but otherwise keeps the
  same "style" as the rest of the file)

Daniel, I took the liberty to keep your "Reviewed-by" tag, as only
patch order and indentation changed.

Frédéric Pétrot (3):
  disas/riscv.c: Correct indent for checkpatch
  disas/riscv.c: Correct wrong shifts for cbo
  disas/riscv.c: Correct disasm of lq

 disas/riscv.c              | 38 +++++++++++++++++++-------------------
 target/riscv/insn32.decode |  2 ++
 2 files changed, 21 insertions(+), 19 deletions(-)

-- 
2.43.0