[PATCH v2 2/3] disas/riscv.c: Correct wrong shifts for cbo

From: Frédéric Pétrot <[email protected]>

The cache block operations are specified on bits 31:20, but for
some reason a shift of 17 and a 5 bit masking were performed.
Make this a raw shift of 20 prior to test for the cbo operation.

Fixes: 9273cda722 ("disas/riscv.c: add 'cbo' insns to disassembler")
Reported-by: Julien Thillard <[email protected]>
Signed-off-by: Frédéric Pétrot <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
---
 disas/riscv.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/disas/riscv.c b/disas/riscv.c
index 689502f083..b32a040745 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -2889,8 +2889,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
             case 2:
                 /*
                  * 'lq' shares the "(...) 010 ..... 0001111" opcode space
-                 * with 'cbo' insns.  Check the next 5 bits to select
-                 * what we want:
+                 * with 'cbo' insns.
                  *
                  * cbo_inval  0000000 00000 ..... 010 00000 0001111
                  * cbo_clean  0000000 00001 ..... 010 00000 0001111
@@ -2899,7 +2898,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
                  *
                  * Anything that doesn't match these will default to 'lq'.
                  */
-                switch ((inst >> 17) & 0b11111) {
+                switch (inst >> 20) {
                 case 0: op = rv_op_cbo_inval; break;
                 case 1: op = rv_op_cbo_clean; break;
                 case 2: op = rv_op_cbo_flush; break;
-- 
2.43.0