Re: [PATCH 04/56] disas/riscv: Decode unsigned vector immediates as unsigned

On Sun, 2026-08-09 at 15:34 -0700, Richard Henderson wrote:
> From: TANG Tiancheng <[email protected]>
> 
> rv_codec_v_i decodes all .vi operands with operand_vimm(), which
> sign-extends bits 19:15. That matches spec operands named imm, but
> not the
> .vi forms whose operand is uimm; uimm=31 is decoded as -1 and printed
> by
> the shared 6-bit 'u' formatter as 63.
> 
> Add rv_codec_v_i_u/operand_vuimm() for the 5-bit uimm forms: vsll.vi,
> vsrl.vi, vsra.vi, vnsrl.wi, vnsra.wi, vssrl.vi, vssra.vi, vnclipu.wi,
> vnclip.wi, vslideup.vi, vslidedown.vi, vrgather.vi, vaeskf1.vi,
> vaeskf2.vi, vsm3c.vi, vsm4k.vi and vwsll.vi. The remaining
> rv_codec_v_i
> entries are the signed imm forms.
> 
> Fixes: 07f4964d1785 ("disas/riscv.c: rvv: Add disas support for
> vector instructions")
> Fixes: 9d92f56d4a44 ("disas/riscv: Add support for vector crypto
> extensions")
> Signed-off-by: TANG Tiancheng <[email protected]>
> Reviewed-by: LIU Zhiwei <[email protected]>
> Message-Id:
> <20260703-b4-disas-xthead-fix-riscv-next-v4-4-84c566330bc7@linux.alib
> aba.com>

Reviewed-by: Alistair Francis <[email protected]>

Alistair

> ---
>  disas/riscv.h |  1 +
>  disas/riscv.c | 45 ++++++++++++++++++++++++++++-----------------
>  2 files changed, 29 insertions(+), 17 deletions(-)
> 
> diff --git a/disas/riscv.h b/disas/riscv.h
> index 379e642ec8..91ada8b531 100644
> --- a/disas/riscv.h
> +++ b/disas/riscv.h
> @@ -149,6 +149,7 @@ typedef enum {
>      rv_codec_v_r,
>      rv_codec_v_ldst,
>      rv_codec_v_i,
> +    rv_codec_v_i_u,
>      rv_codec_vsetvli,
>      rv_codec_vsetivli,
>      rv_codec_vror_vi,
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 967739bdbb..82b962dc71 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -1803,19 +1803,19 @@ const rv_opcode_data rvi_opcode_data[] = {
>      { "vxor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0
> },
>      { "vsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
>      { "vsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> -    { "vsll.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0
> },
> +    { "vsll.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0,
> 0 },
>      { "vsrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
>      { "vsrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> -    { "vsrl.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0
> },
> +    { "vsrl.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0,
> 0 },
>      { "vsra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
>      { "vsra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> -    { "vsra.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0
> },
> +    { "vsra.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0,
> 0 },
>      { "vnsrl.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
>      { "vnsrl.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> -    { "vnsrl.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0
> },
> +    { "vnsrl.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0,
> 0 },
>      { "vnsra.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
>      { "vnsra.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> -    { "vnsra.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0
> },
> +    { "vnsra.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0,
> 0 },
>      { "vmseq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
>      { "vmseq.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
>      { "vmseq.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0
> },
> @@ -1909,16 +1909,16 @@ const rv_opcode_data rvi_opcode_data[] = {
>      { "vsmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
>      { "vssrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
>      { "vssrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> -    { "vssrl.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0
> },
> +    { "vssrl.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0,
> 0 },
>      { "vssra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
>      { "vssra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> -    { "vssra.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0
> },
> +    { "vssra.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0,
> 0 },
>      { "vnclipu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0,
> 0 },
>      { "vnclipu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0,
> 0 },
> -    { "vnclipu.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0,
> 0 },
> +    { "vnclipu.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0,
> 0, 0 },
>      { "vnclip.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
>      { "vnclip.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> -    { "vnclip.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0,
> 0 },
> +    { "vnclip.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0,
> 0, 0 },
>      { "vfadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
>      { "vfadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0
> },
>      { "vfsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> @@ -2048,15 +2048,15 @@ const rv_opcode_data rvi_opcode_data[] = {
>      { "vfmv.f.s", rv_codec_v_r, rv_fmt_fd_vs2, NULL, 0, 0, 0 },
>      { "vfmv.s.f", rv_codec_v_r, rv_fmt_vd_fs1, NULL, 0, 0, 0 },
>      { "vslideup.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0,
> 0 },
> -    { "vslideup.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0,
> 0, 0 },
> +    { "vslideup.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0,
> 0, 0 },
>      { "vslide1up.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0,
> 0, 0 },
>      { "vslidedown.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0,
> 0, 0 },
> -    { "vslidedown.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0,
> 0, 0 },
> +    { "vslidedown.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL,
> 0, 0, 0 },
>      { "vslide1down.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0,
> 0, 0 },
>      { "vrgather.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0,
> 0 },
>      { "vrgatherei16.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL,
> 0, 0, 0 },
>      { "vrgather.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0,
> 0 },
> -    { "vrgather.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0,
> 0, 0 },
> +    { "vrgather.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0,
> 0, 0 },
>      { "vcompress.vm", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0
> },
>      { "vmv1r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
>      { "vmv2r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
> @@ -2144,8 +2144,8 @@ const rv_opcode_data rvi_opcode_data[] = {
>      { "vaesef.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
>      { "vaesem.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
>      { "vaesem.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
> -    { "vaeskf1.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0
> },
> -    { "vaeskf2.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0
> },
> +    { "vaeskf1.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm, NULL, 0, 0,
> 0 },
> +    { "vaeskf2.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm, NULL, 0, 0,
> 0 },
>      { "vaesz.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
>      { "vandn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
>      { "vandn.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> @@ -2169,14 +2169,14 @@ const rv_opcode_data rvi_opcode_data[] = {
>      { "vsha2ch.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0
> },
>      { "vsha2cl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0
> },
>      { "vsha2ms.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0
> },
> -    { "vsm3c.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 },
> +    { "vsm3c.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0
> },
>      { "vsm3me.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 },
> -    { "vsm4k.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 },
> +    { "vsm4k.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0
> },
>      { "vsm4r.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
>      { "vsm4r.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
>      { "vwsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
>      { "vwsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> -    { "vwsll.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0
> },
> +    { "vwsll.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0,
> 0 },
>      { "amocas.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0,
> 0 },
>      { "amocas.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0,
> 0 },
>      { "amocas.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0,
> 0 },
> @@ -4492,6 +4492,11 @@ static int32_t operand_vimm(rv_inst inst)
>      return (int64_t)(inst << 44) >> 59;
>  }
>  
> +static uint32_t operand_vuimm(rv_inst inst)
> +{
> +    return extract32(inst, 15, 5);
> +}
> +
>  static uint32_t operand_vzimm11(rv_inst inst)
>  {
>      return (inst << 33) >> 53;
> @@ -4895,6 +4900,12 @@ static void decode_inst_operands(rv_decode
> *dec, rv_isa isa)
>          dec->imm = operand_vimm(inst);
>          dec->vm = operand_vm(inst);
>          break;
> +    case rv_codec_v_i_u:
> +        dec->rd = operand_rd(inst);
> +        dec->rs2 = operand_rs2(inst);
> +        dec->imm = operand_vuimm(inst);
> +        dec->vm = operand_vm(inst);
> +        break;
>      case rv_codec_vror_vi:
>          dec->rd = operand_rd(inst);
>          dec->rs2 = operand_rs2(inst);