Re: [PATCH 07/56] disas/riscv: Reduce rv_insn to uint32_t

On Sun, 2026-08-09 at 15:34 -0700, Richard Henderson wrote:
> Since 758dce9c98a, the only possible values for
> instruction length are 2 and 4.
> 
> Signed-off-by: Richard Henderson <[email protected]>

Reviewed-by: Alistair Francis <[email protected]>

Alistair

> ---
>  disas/riscv.h |  2 +-
>  disas/riscv.c | 12 +++---------
>  2 files changed, 4 insertions(+), 10 deletions(-)
> 
> diff --git a/disas/riscv.h b/disas/riscv.h
> index 91ada8b531..eabe193b4f 100644
> --- a/disas/riscv.h
> +++ b/disas/riscv.h
> @@ -11,7 +11,7 @@
>  
>  /* types */
>  
> -typedef uint64_t rv_inst;
> +typedef uint32_t rv_inst;
>  typedef uint16_t rv_opcode;
>  
>  /* enums */
> diff --git a/disas/riscv.c b/disas/riscv.c
> index e3fbc26626..012f90fce6 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -5491,10 +5491,8 @@ static GString *disasm_inst(rv_isa isa,
> uint64_t pc, rv_inst inst,
>      return format_inst(24, &dec);
>  }
>  
> -#define INST_FMT_2 "%04" PRIx64 "              "
> -#define INST_FMT_4 "%08" PRIx64 "          "
> -#define INST_FMT_6 "%012" PRIx64 "      "
> -#define INST_FMT_8 "%016" PRIx64 "  "
> +#define INST_FMT_2 "%04x              "
> +#define INST_FMT_4 "%08x          "
>  
>  static int
>  print_insn_riscv(bfd_vma memaddr, struct disassemble_info *info,
> rv_isa isa)
> @@ -5530,12 +5528,8 @@ print_insn_riscv(bfd_vma memaddr, struct
> disassemble_info *info, rv_isa isa)
>          case 4:
>              (*info->fprintf_func)(info->stream, INST_FMT_4, inst);
>              break;
> -        case 6:
> -            (*info->fprintf_func)(info->stream, INST_FMT_6, inst);
> -            break;
>          default:
> -            (*info->fprintf_func)(info->stream, INST_FMT_8, inst);
> -            break;
> +            g_assert_not_reached();
>          }
>      }
>