Re: [PATCH 09/56] disas/riscv: Pass rv_opcode_data pointer to decode_inst_operands
Alistair <[email protected]>
| Newsgroups | org.nongnu.qemu-riscv,org.nongnu.qemu-devel |
|---|---|
| Message-ID | <[email protected]> |
On Sun, 2026-08-09 at 15:34 -0700, Richard Henderson wrote: > Signed-off-by: Richard Henderson <[email protected]> Reviewed-by: Alistair Francis <[email protected]> Alistair > --- > disas/riscv.c | 12 ++++++++---- > 1 file changed, 8 insertions(+), 4 deletions(-) > > diff --git a/disas/riscv.c b/disas/riscv.c > index 986dc6b752..af43940732 100644 > --- a/disas/riscv.c > +++ b/disas/riscv.c > @@ -4595,11 +4595,12 @@ static void decode_inst_opcode(rv_decode > *dec, rv_isa isa) > > /* decode operands */ > > -static void decode_inst_operands(rv_decode *dec, rv_isa isa) > +static void decode_inst_operands(rv_decode *dec, rv_isa isa, > + const rv_opcode_data *op) > { > - const rv_opcode_data *opcode_data = dec->opcode_data; > rv_inst inst = dec->inst; > - dec->codec = opcode_data[dec->op].codec; > + > + dec->codec = op->codec; > switch (dec->codec) { > case rv_codec_none: > dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero; > @@ -5468,6 +5469,8 @@ static GString *disasm_inst(rv_isa isa, > uint64_t pc, rv_inst inst, > { has_xlrbr_p, rv_xlrbr_opcode_data, decode_xlrbr }, > }; > > + const rv_opcode_data *op; > + > for (size_t i = 0; i < ARRAY_SIZE(decoders); i++) { > bool (*guard_func)(const RISCVCPUConfig *) = > decoders[i].guard_func; > const rv_opcode_data *opcode_data = decoders[i].opcode_data; > @@ -5486,7 +5489,8 @@ static GString *disasm_inst(rv_isa isa, > uint64_t pc, rv_inst inst, > dec.opcode_data = rvi_opcode_data; > } > > - decode_inst_operands(&dec, isa); > + op = &dec.opcode_data[dec.op]; > + decode_inst_operands(&dec, isa, op); > decode_inst_decompress(&dec, isa); > decode_inst_lift_pseudo(&dec); > return format_inst(24, &dec);