Re: [PATCH 19/56] disas/riscv: Simplify c.addi

On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote:
> While c.addi with imm == 0 and rd == 0 is c.nop,
> other c.addi with imm == 0 and rd != 0 are not illegal,
> but are reserved as HINTs.  Go ahead and disassemble as
> c.addi rather than falling back to invalid.
> 
> Further, there's no reason to differentiate c.nop, since we have
>   c.addi -> addi -> nop
> vs
>   c.nop -> addi -> nop
> via decompress and pseudo translation steps.
> 
> Signed-off-by: Richard Henderson <[email protected]>

Reviewed-by: Alistair Francis <[email protected]>

Alistair

> ---
>  disas/riscv.c | 11 +++--------
>  1 file changed, 3 insertions(+), 8 deletions(-)
> 
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 8a957e6a1e..7978ffb378 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -263,7 +263,6 @@ typedef enum {
>      rv_op_c_fsd = 231,
>      rv_op_c_sw = 232,
>      rv_op_c_fsw = 233,
> -    rv_op_c_nop = 234,
>      rv_op_c_addi = 235,
>      rv_op_c_jal = 236,
>      rv_op_c_li = 237,
> @@ -1896,10 +1895,9 @@ static const rv_opcode_data rvi_opcode_data[]
> = {
>      { "c.sw", rv_codec_cs_sw, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw,
> rv_op_sw,
>        rv_op_sw },
>      { "c.fsw", rv_codec_cs_sw, rv_fmt_frs2_offset_rs1, NULL,
> rv_op_fsw, 0, 0 },
> -    { "c.nop", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_addi,
> rv_op_addi,
> -      rv_op_addi },
> +    { },
>      { "c.addi", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, rv_op_addi,
> rv_op_addi,
> -      rv_op_addi, rvcd_imm_nz },
> +      rv_op_addi },
>      { "c.jal", rv_codec_cj_jal, rv_fmt_rd_offset, NULL, rv_op_jal,
> 0, 0 },
>      { "c.li", rv_codec_ci_li, rv_fmt_rd_rs1_imm, NULL, rv_op_addi,
> rv_op_addi,
>        rv_op_addi },
> @@ -3010,10 +3008,7 @@ static void decode_inst_opcode(rv_decode *dec,
> rv_isa isa)
>      case 1:
>          switch ((inst >> 13) & 0b111) {
>          case 0:
> -            switch ((inst >> 2) & 0b11111111111) {
> -            case 0: op = rv_op_c_nop; break;
> -            default: op = rv_op_c_addi; break;
> -            }
> +            op = rv_op_c_addi; /* or unspecified HINT */
>              break;
>          case 1:
>              if (isa == rv32) {