Re: [PATCH 18/56] disas/riscv: Handle c.addi4spn imm != 0 during decode

On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <[email protected]>

Reviewed-by: Alistair Francis <[email protected]>

Alistair

> ---
>  disas/riscv.c | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 9813d75feb..8a957e6a1e 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -1885,7 +1885,7 @@ static const rv_opcode_data rvi_opcode_data[] =
> {
>      { "fmv.x.q", rv_codec_r, rv_fmt_rd_frs1 },
>      { "fmv.q.x", rv_codec_r, rv_fmt_frd_rs1 },
>      { "c.addi4spn", rv_codec_ciw_4spn, rv_fmt_rd_rs1_imm, NULL,
> rv_op_addi,
> -      rv_op_addi, rv_op_addi, rvcd_imm_nz },
> +      rv_op_addi, rv_op_addi },
>      { "c.fld", rv_codec_cl_ld, rv_fmt_frd_offset_rs1, NULL,
> rv_op_fld,
>        rv_op_fld, 0 },
>      { "c.lw", rv_codec_cl_lw, rv_fmt_rd_offset_rs1, NULL, rv_op_lw,
> rv_op_lw,
> @@ -2952,7 +2952,11 @@ static void decode_inst_opcode(rv_decode *dec,
> rv_isa isa)
>      switch ((inst >> 0) & 0b11) {
>      case 0:
>          switch ((inst >> 13) & 0b111) {
> -        case 0: op = rv_op_c_addi4spn; break;
> +        case 0:
> +            if ((inst >> 5) & 0xff) {
> +                op = rv_op_c_addi4spn;
> +            }
> +            break;
>          case 1:
>              if (isa == rv128) {
>                  op = rv_op_c_lq;