Re: [PATCH 28/56] disas/riscv: Handle aliases of csrrs during decode

On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <[email protected]>

Reviewed-by: Alistair Francis <[email protected]>

Alistair

> ---
>  disas/riscv.h |  7 -----
>  disas/riscv.c | 85 +++++++++++--------------------------------------
> --
>  2 files changed, 17 insertions(+), 75 deletions(-)
> 
> diff --git a/disas/riscv.h b/disas/riscv.h
> index 900363c603..d8c5acd969 100644
> --- a/disas/riscv.h
> +++ b/disas/riscv.h
> @@ -86,13 +86,6 @@ typedef enum {
>      rvc_imm_eq_p1,
>      rvc_csr_eq_0x001,
>      rvc_csr_eq_0x002,
> -    rvc_csr_eq_0x003,
> -    rvc_csr_eq_0xc00,
> -    rvc_csr_eq_0xc01,
> -    rvc_csr_eq_0xc02,
> -    rvc_csr_eq_0xc80,
> -    rvc_csr_eq_0xc81,
> -    rvc_csr_eq_0xc82,
>  } rvc_constraint;
>  
>  typedef enum {
> diff --git a/disas/riscv.c b/disas/riscv.c
> index e464b8b075..9ec79baf4d 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -1063,24 +1063,6 @@ static const rvc_constraint rvcc_ret[] = {
> rvc_rd_eq_x0, rvc_rs1_eq_ra,
>                                             rvc_end };
>  static const rvc_constraint rvcc_jr[] = { rvc_rd_eq_x0,
> rvc_imm_eq_zero,
>                                            rvc_end };
> -static const rvc_constraint rvcc_rdcycle[] = { rvc_rs1_eq_x0,
> rvc_csr_eq_0xc00,
> -                                               rvc_end };
> -static const rvc_constraint rvcc_rdtime[] = { rvc_rs1_eq_x0,
> rvc_csr_eq_0xc01,
> -                                              rvc_end };
> -static const rvc_constraint rvcc_rdinstret[] = { rvc_rs1_eq_x0,
> -                                                 rvc_csr_eq_0xc02,
> rvc_end };
> -static const rvc_constraint rvcc_rdcycleh[] = { rvc_rs1_eq_x0,
> -                                                rvc_csr_eq_0xc80,
> rvc_end };
> -static const rvc_constraint rvcc_rdtimeh[] = { rvc_rs1_eq_x0,
> rvc_csr_eq_0xc81,
> -                                               rvc_end };
> -static const rvc_constraint rvcc_rdinstreth[] = { rvc_rs1_eq_x0,
> -                                                  rvc_csr_eq_0xc82,
> rvc_end };
> -static const rvc_constraint rvcc_frcsr[] = { rvc_rs1_eq_x0,
> rvc_csr_eq_0x003,
> -                                             rvc_end };
> -static const rvc_constraint rvcc_frrm[] = { rvc_rs1_eq_x0,
> rvc_csr_eq_0x002,
> -                                            rvc_end };
> -static const rvc_constraint rvcc_frflags[] = { rvc_rs1_eq_x0,
> rvc_csr_eq_0x001,
> -                                               rvc_end };
>  static const rvc_constraint rvcc_fsrmi[] = { rvc_csr_eq_0x002,
> rvc_end };
>  static const rvc_constraint rvcc_fsflagsi[] = { rvc_csr_eq_0x001,
> rvc_end };
>  
> @@ -1163,19 +1145,6 @@ static const rv_comp_data rvcp_subw[] = {
>      { rv_op_illegal, NULL }
>  };
>  
> -static const rv_comp_data rvcp_csrrs[] = {
> -    { rv_op_rdcycle, rvcc_rdcycle },
> -    { rv_op_rdtime, rvcc_rdtime },
> -    { rv_op_rdinstret, rvcc_rdinstret },
> -    { rv_op_rdcycleh, rvcc_rdcycleh },
> -    { rv_op_rdtimeh, rvcc_rdtimeh },
> -    { rv_op_rdinstreth, rvcc_rdinstreth },
> -    { rv_op_frcsr, rvcc_frcsr },
> -    { rv_op_frrm, rvcc_frrm },
> -    { rv_op_frflags, rvcc_frflags },
> -    { rv_op_illegal, NULL }
> -};
> -
>  static const rv_comp_data rvcp_csrrwi[] = {
>      { rv_op_fsrmi, rvcc_fsrmi },
>      { rv_op_fsflagsi, rvcc_fsflagsi },
> @@ -1751,7 +1720,7 @@ static const rv_opcode_data rvi_opcode_data[] =
> {
>      { "sfence.vma", rv_codec_r, rv_fmt_rs1_rs2 },
>      { "wfi", rv_codec_none, rv_fmt_none },
>      { "csrrw", rv_codec_i_csr, rv_fmt_rd_csr_rs1 },
> -    { "csrrs", rv_codec_i_csr, rv_fmt_rd_csr_rs1, rvcp_csrrs },
> +    { "csrrs", rv_codec_i_csr, rv_fmt_rd_csr_rs1 },
>      { "csrrc", rv_codec_i_csr, rv_fmt_rd_csr_rs1 },
>      { "csrrwi", rv_codec_i_csr, rv_fmt_rd_csr_zimm, rvcp_csrrwi },
>      { "csrrsi", rv_codec_i_csr, rv_fmt_rd_csr_zimm },
> @@ -4440,7 +4409,22 @@ static void decode_inst_opcode(rv_decode *dec,
> rv_isa isa)
>                  default: op = rv_op_csrrw; break;
>                  }
>                  break;
> -            case 2: op = rv_op_csrrs; break;
> +            case 2:
> +                op = rv_op_csrrs;
> +                if (operand_rs1(inst) == 0) {
> +                    switch (operand_csr12(inst)) {
> +                    case 0x001: op = rv_op_frflags; break;
> +                    case 0x002: op = rv_op_frrm; break;
> +                    case 0x003: op = rv_op_frcsr; break;
> +                    case 0xc00: op = rv_op_rdcycle; break;
> +                    case 0xc01: op = rv_op_rdtime; break;
> +                    case 0xc02: op = rv_op_rdinstret; break;
> +                    case 0xc80: op = rv_op_rdcycleh; break;
> +                    case 0xc81: op = rv_op_rdtimeh; break;
> +                    case 0xc82: op = rv_op_rdinstreth; break;
> +                    }
> +                }
> +                break;
>              case 3: op = rv_op_csrrc; break;
>              case 4:
>                  if (dec->cfg && dec->cfg->ext_zimop) {
> @@ -5017,41 +5001,6 @@ static bool check_constraints(rv_decode *dec,
> const rvc_constraint *c)
>                  return false;
>              }
>              break;
> -        case rvc_csr_eq_0x003:
> -            if (!(imm == 0x003)) {
> -                return false;
> -            }
> -            break;
> -        case rvc_csr_eq_0xc00:
> -            if (!(imm == 0xc00)) {
> -                return false;
> -            }
> -            break;
> -        case rvc_csr_eq_0xc01:
> -            if (!(imm == 0xc01)) {
> -                return false;
> -            }
> -            break;
> -        case rvc_csr_eq_0xc02:
> -            if (!(imm == 0xc02)) {
> -                return false;
> -            }
> -            break;
> -        case rvc_csr_eq_0xc80:
> -            if (!(imm == 0xc80)) {
> -                return false;
> -            }
> -            break;
> -        case rvc_csr_eq_0xc81:
> -            if (!(imm == 0xc81)) {
> -                return false;
> -            }
> -            break;
> -        case rvc_csr_eq_0xc82:
> -            if (!(imm == 0xc82)) {
> -                return false;
> -            }
> -            break;
>          default: break;
>          }
>          c++;