Re: [PATCH 29/56] disas/riscv: Handle aliases of csrrwi during decode
Alistair <[email protected]>
| Newsgroups | org.nongnu.qemu-riscv,org.nongnu.qemu-devel |
|---|---|
| Message-ID | <[email protected]> |
On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote: > Signed-off-by: Richard Henderson <[email protected]> Reviewed-by: Alistair Francis <[email protected]> Alistair > --- > disas/riscv.h | 2 -- > disas/riscv.c | 28 ++++++++-------------------- > 2 files changed, 8 insertions(+), 22 deletions(-) > > diff --git a/disas/riscv.h b/disas/riscv.h > index d8c5acd969..3bbcbf10fb 100644 > --- a/disas/riscv.h > +++ b/disas/riscv.h > @@ -84,8 +84,6 @@ typedef enum { > rvc_imm_eq_zero, > rvc_imm_eq_n1, > rvc_imm_eq_p1, > - rvc_csr_eq_0x001, > - rvc_csr_eq_0x002, > } rvc_constraint; > > typedef enum { > diff --git a/disas/riscv.c b/disas/riscv.c > index 9ec79baf4d..d3cbfb86ac 100644 > --- a/disas/riscv.c > +++ b/disas/riscv.c > @@ -1063,8 +1063,6 @@ static const rvc_constraint rvcc_ret[] = { > rvc_rd_eq_x0, rvc_rs1_eq_ra, > rvc_end }; > static const rvc_constraint rvcc_jr[] = { rvc_rd_eq_x0, > rvc_imm_eq_zero, > rvc_end }; > -static const rvc_constraint rvcc_fsrmi[] = { rvc_csr_eq_0x002, > rvc_end }; > -static const rvc_constraint rvcc_fsflagsi[] = { rvc_csr_eq_0x001, > rvc_end }; > > /* pseudo-instruction metadata */ > > @@ -1145,12 +1143,6 @@ static const rv_comp_data rvcp_subw[] = { > { rv_op_illegal, NULL } > }; > > -static const rv_comp_data rvcp_csrrwi[] = { > - { rv_op_fsrmi, rvcc_fsrmi }, > - { rv_op_fsflagsi, rvcc_fsflagsi }, > - { rv_op_illegal, NULL } > -}; > - > static const rv_comp_data rvcp_fsgnj_s[] = { > { rv_op_fmv_s, rvcc_fmv_s }, > { rv_op_illegal, NULL } > @@ -1722,7 +1714,7 @@ static const rv_opcode_data rvi_opcode_data[] = > { > { "csrrw", rv_codec_i_csr, rv_fmt_rd_csr_rs1 }, > { "csrrs", rv_codec_i_csr, rv_fmt_rd_csr_rs1 }, > { "csrrc", rv_codec_i_csr, rv_fmt_rd_csr_rs1 }, > - { "csrrwi", rv_codec_i_csr, rv_fmt_rd_csr_zimm, rvcp_csrrwi }, > + { "csrrwi", rv_codec_i_csr, rv_fmt_rd_csr_zimm }, > { "csrrsi", rv_codec_i_csr, rv_fmt_rd_csr_zimm }, > { "csrrci", rv_codec_i_csr, rv_fmt_rd_csr_zimm }, > { "flw", rv_codec_i, rv_fmt_frd_offset_rs1 }, > @@ -4469,7 +4461,13 @@ static void decode_inst_opcode(rv_decode *dec, > rv_isa isa) > } > } > break; > - case 5: op = rv_op_csrrwi; break; > + case 5: > + switch (operand_csr12(inst)) { > + case 1: op = rv_op_fsflagsi; break; > + case 2: op = rv_op_fsrmi; break; > + default: op = rv_op_csrrwi; break; > + } > + break; > case 6: op = rv_op_csrrsi; break; > case 7: op = rv_op_csrrci; break; > } > @@ -4991,16 +4989,6 @@ static bool check_constraints(rv_decode *dec, > const rvc_constraint *c) > return false; > } > break; > - case rvc_csr_eq_0x001: > - if (!(imm == 0x001)) { > - return false; > - } > - break; > - case rvc_csr_eq_0x002: > - if (!(imm == 0x002)) { > - return false; > - } > - break; > default: break; > } > c++;