Re: [PATCH 1/2] riscv: csr: do not drop C bit on misa write

On Thu, 2026-08-06 at 16:37 +0300, Vladimir Isaev wrote:
> According to spec:
> > Writing misa may increase IALIGN, e.g., by disabling the "C"
> > extension.
> > If an instruction that would write misa increases IALIGN, and the
> > subsequent instruction’s address is not IALIGN-bit aligned, the
> > write to misa is suppressed, leaving misa unchanged.
> 
> So attempt to disable C extension if next instruction is not aligned
> should not
> change the misa.
> 
> Signed-off-by: Vladimir Isaev <[email protected]>

Reviewed-by: Alistair Francis <[email protected]>

Thanks for the patches.

Can you please re-send the series with a cover-letter. All multi-patch
series should have a cover letter

Alistair

> ---
>  target/riscv/tcg/csr.c | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c
> index 36f2004bc5..58c206c1fa 100644
> --- a/target/riscv/tcg/csr.c
> +++ b/target/riscv/tcg/csr.c
> @@ -2182,9 +2182,10 @@ static RISCVException write_misa(CPURISCVState
> *env, int csrno,
>      /* Mask extensions that are not supported by this hart */
>      val &= env->misa_ext_mask;
>  
> -    /* Suppress 'C' if next instruction is not aligned. */
> -    if ((val & RVC) && (get_next_pc(env, ra) & 3) != 0) {
> -        val &= ~RVC;
> +    /* drop write if RVC is cleared and next instruction is not
> aligned */
> +    if ((env->misa_ext & RVC) && !(val & RVC) &&
> +         (get_next_pc(env, ra) & 3) != 0) {
> +        return RISCV_EXCP_NONE;
>      }
>  
>      /* Disable RVG if any of its dependencies are disabled */